Storage and accessing methods for parameters in streaming AI accelerator chip
The present disclosure provides storage and accessing methods for parameters in a streaming AI accelerator chip, and relates to the technical field of artificial intelligence, wherein the streaming-based data buffer comprises: a plurality of banks, different banks being configured to store different data; a data read circuit configured to receive a read control signal and a read address corresponding to a computation task, in the case the read control signal corresponds to a first read mode, determine n banks from the plurality of banks based on the read control signal, and read first data required for performing the computation task in parallel from the n banks based on the read address, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer.
1. A streaming-based data buffer comprising:
a plurality of banks, different banks being configured to store different data;
a data read circuit configured to receive a read control signal and a read address corresponding to a computation task, in the case the read control signal corresponds to a first read mode, determine n banks from the plurality of banks based on the read control signal, and read a first data required for performing the computation task in parallel from the n banks based on the read address, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer;
wherein the read address comprises an addressing address and a chip select address, the data read circuit is configured to read the first data based on the addressing address;
the data read circuit is further configured to, in the case the read control signal corresponds to a second read mode, determine one bank from the plurality of banks based on the chip select address and read a second data required for performing the computation task from the one bank based on the addressing address; and
the read control signal corresponds to the second read mode in the case the computation task is a bilinear interpolation in the neural network algorithm.
2. The data buffer of claim 1 , wherein the read control signal corresponds to the first read mode in the case the computation task is a convolution.
3. The data buffer of claim 2 , wherein in the case the computation task is a standard convolution in a neural network algorithm, each piece of the data comprises part of the data in one convolution kernel.
4. The data buffer of claim 2 , wherein in the case the computation task is a depth separable convolution in the neural network algorithm, each piece of the data comprises part of data in a feature map of one channel.
5. The data buffer of claim 1 , further comprising:
a data write circuit configured to receive a write control signal and a write address corresponding to the computation task, determine the n banks based on the write control signal and write the first data in parallel to the n banks based on the write address in the case the write control signal corresponds to a first write mode.
6. A streaming-based data processing method, comprising:
using the data buffer of claim 1 , wherein the data read circuit of the data buffer:
receiving a read control signal and a read address corresponding to a computation task;
in the case the read control signal corresponds to a first read mode, determining n banks from the plurality of banks based on the read control signal, and reading a first data required for performing the computation task in parallel from the n banks based on the read address, different data being stored in different banks of the plurality of banks, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer.
7. The streaming-based data processing method of claim 6 , wherein the read address comprises an addressing address and a chip select address, and the reading the first data required for performing the computation task from the n banks in parallel based on the read address comprises:
reading the first data based on the addressing address.
8. The streaming-based data processing method of claim 7 , further comprising:
in the case the read control signal corresponds to a second read mode, determining one bank from the plurality of banks based on the chip select address and read a second data required for performing the computation task from the one bank based on the addressing address.
9. The streaming-based data processing method of claim 6 , further comprising:
receiving a write control signal and a write address corresponding to the computation task;
determining the n banks based on the write control signal and write the first data in parallel to the n banks based on the write address in the case the write control signal corresponds to a first write mode.
10. An artificial intelligence chip comprising:
the streaming-based data buffer of claim 1 ;
an address generation unit configured to generate the read address and send the read address to the data buffer in response to a first drive signal corresponding to the computation task; and
a control register configured to send the read control signal to the data buffer and send the first drive signal to the address generation unit in response to a first configuration signal corresponding to the computation task.