Circuit and method for calibration of a digital-to-analog converter

1. A digital-to-analog converter (DAC), comprising:

a plurality of unit cells configured to receive a digital input from a processing circuit and convert the digital input to analog outputs,

an engine configured to:

designate one of the plurality of unit cells as a reference cell with a first value; and

calibrate the first value using a value of the unit cells, wherein the value is a delay value,

wherein the digital input is provided to a first unit cell and has an opposite sign to the digital input provided to the reference cell.

2. The DAC of claim 1 , wherein the engine is configured to calibrate the remainder of the plurality of unit cells to match the first value.

3. The DAC of claim 1 , wherein analog outputs are combined to create an overall analog output by summing a second analog output at least from a first analog output, wherein the overall analog output comprises a combination of analog outputs from the plurality of unit cells.

4. The DAC of claim 1 , wherein the first value and the lowest or highest value is at least one of an amplitude of the analog outputs and a timing of the analog outputs.

5. The DAC of claim 1 , wherein the DAC is part of a transmitter for wireless communication.

6. A method for calibrating a digital-to-analog converter (DAC), the method comprising:

designating one of a plurality of DAC unit cells as a reference cell;

adjusting the reference cell to have a first value for an output signal at a first output;

comparing output signals at the outputs of remaining DAC unit cells of the plurality of DAC unit cells with the first output; and

adjusting the remaining DAC unit cells of the plurality of DAC unit cells in accordance with the first value.

7. The method of claim 6 , wherein the comparing uses a first digital input at one of the remaining DAC unit cells, wherein the first digital input is at least one of a current signal and a voltage signal.

8. The method of claim 6 , wherein the first value is a lowest or highest value of amplitude of the output signals at the outputs.

9. The method of claim 6 , wherein the first value is a lowest or highest value of amplitude or speed of the output signals at the outputs.

10. The method of claim 9 , wherein the lowest value of speed is a longest delay or the highest value of speed is the shortest delay.

11. The method of claim 6 , wherein the DAC is a transmitter for wireless communication.

12. The method of claim 6 , wherein adjusting provides a change to a drive strength.

13. A calibration system for a digital-to-analog converter (DAC), the DAC being configured to receive, by a plurality of DAC unit cells, a digital input and convert the digital input to analog signals, the analog signals being summed as an output signal, the calibration system, comprising:

a detector configured to determine a difference between a first value of a first cell of the DAC unit cells to a reference value of a reference cell at a summed output associated with the output signal; and

a calibration engine configured to adjust the first cell to have the first value match the reference value in response to an error.

14. The calibration system of claim 13 , wherein the digital input is at least one of a current signal and a voltage signal and wherein the reference value is a lowest or highest value in amplitude or speed provided by the plurality of DAC unit cells.

15. The calibration system of claim 13 , wherein the reference cell and the first cell receive opposite digital inputs.

16. The calibration system of claim 13 , wherein the detector and the calibration engine are used to adjust the remaining cells of the plurality of DAC unit cells.

17. The calibration system of claim 13 , wherein the DAC is a transmitter for wireless communication and is provided on an integrated circuit including the calibration engine.

18. The calibration system of claim 13 , wherein the reference cell is one of the plurality of DAC unit cells.

19. A digital-to-analog converter (DAC), comprising:

a plurality of unit cells configured to receive a digital input from a processing circuit and convert the digital input to analog outputs;

an engine configured to:

designate one of the plurality of unit cells as a reference cell with a first value;

calibrate the first value using a lowest or highest value of the unit cells; and

wherein the digital input is provided to a first unit cell and has an opposite sign to the digital input provided to the reference cell.

20. The DAC of claim 19 , wherein the lowest value is a delay value.