Continuous-time delta-sigma modulator
A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.
1. A continuous-time delta-sigma modulator (CT-DSM) comprising:
a loop filter configured to generate a first intermediate signal according to an input signal, a feedback signal, and a compensation signal;
a pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) coupled to the loop filter and configured to generate a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal;
a feedback circuit coupled to the pipelined SAR ADC and configured to generate the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal;
an excess loop delay (ELD) compensation circuit coupled to the feedback circuit and the loop filter and configured to generate the compensation signal according to at least one output signal of the feedback circuit; and
a logic circuit coupled to the pipelined SAR ADC and configured to generate an output digital code according to the first digital code and the second digital code.
2. The CT-DSM of claim 1 , wherein the pipelined SAR ADC comprises:
a first SAR ADC configured to generate the first digital code and the first quantization error signal according to the first intermediate signal;
a second SAR ADC configured to generate the second digital code and the second quantization error signal according to a second intermediate signal; and
a delay and amplifier circuit coupled to the first SAR ADC and the second SAR ADC and configured to generate the second intermediate signal according to the first quantization error signal and the second quantization error signal.
3. The CT-DSM of claim 2 , wherein the delay and amplifier circuit comprises:
a delay circuit group coupled to the second SAR ADC and configured to delay the second quantization error signal to generate a plurality of delayed signals; and
an amplifier coupled to the delay circuit group and the first SAR ADC and configured to amplify the first quantization error signal and the delayed signals to generate the second intermediate signal.
4. The CT-DSM of claim 3 , wherein the amplifier comprises:
a first switch;
a second switch;
a first capacitor;
a second capacitor;
a first input transistor pair including a first transistor and a second transistor, wherein the first transistor has a first control terminal, a first source, and a first drain, the second transistor has a second control terminal, a second source, and a second drain, and the first source is coupled to the second source;
a second input transistor pair including a third transistor and a fourth transistor, wherein the third transistor has a third control terminal, a third source, and a third drain, the fourth transistor has a fourth control terminal, a fourth source, and a fourth drain, and the third source is coupled to the fourth source;
a fifth transistor having a fifth control terminal, a fifth source, and a fifth drain, wherein the fifth control terminal receives a clock, the fifth drain is coupled to the first drain and the third drain, and the fifth source receives a power supply voltage;
a sixth transistor having a sixth control terminal, a sixth source, and a sixth drain, wherein the sixth control terminal receives the clock, the sixth drain is coupled to the second drain and the fourth drain, and the sixth source receives the power supply voltage;
a seventh transistor having a seventh control terminal, a seventh source, and a seventh drain, wherein the seventh control terminal receives a reset signal, the seventh drain is coupled to the first capacitor and coupled to the first drain, the third drain, and the fifth drain through the first switch, and the seventh source receives the power supply voltage;
an eighth transistor having an eighth control terminal, an eighth source, and an eighth drain, wherein the eighth control terminal receives the reset signal, the eighth drain is coupled to the second capacitor and coupled to the second drain, the fourth drain, and the sixth drain through the second switch, and the eighth source receives the power supply voltage;
a ninth transistor having a ninth control terminal, a ninth source, and a ninth drain; and
a tenth transistor having a tenth control terminal, a tenth source, and a tenth drain, wherein the tenth control terminal receives the clock, the tenth drain is coupled to the first source, the second source, the third source, and the fourth source, and the tenth source is coupled to a reference voltage through the ninth transistor.
5. The CT-DSM of claim 4 , wherein the amplifier further comprises:
a third capacitor;
a fourth capacitor,
an eleventh transistor having an eleventh control terminal, an eleventh source, and an eleventh drain, wherein the eleventh control terminal is coupled to the sixth drain of the sixth transistor, the eleventh source is coupled to the third capacitor, and the eleventh drain is coupled to the fifth drain of the fifth transistor;
a twelfth transistor having a twelfth control terminal, a twelfth source, and a twelfth drain, wherein the twelfth control terminal is coupled to the fifth drain of the fifth transistor, the twelfth source is coupled to the fourth capacitor, and the twelfth drain is coupled to the sixth drain of the sixth transistor;
a thirteenth transistor having a thirteenth control terminal, a thirteenth source, and a thirteenth drain, wherein the thirteenth control terminal receives the clock, the thirteenth drain is coupled to the third capacitor, and the thirteenth source receives the power supply voltage; and
a fourteenth transistor having a fourteenth control terminal, a fourteenth source, and a fourteenth drain, wherein the fourteenth control terminal receives the clock, the fourteenth drain is coupled to the fourth capacitor, and the fourteenth source receives the power supply voltage.
6. The CT-DSM of claim 3 , wherein the delay circuit group comprises:
a first delay circuit configured to delay the second quantization error signal by a first time period; and
a second delay circuit configured to delay the second quantization error signal by a second time period;
wherein the first time period is different from the second time period.
7. The CT-DSM of claim 1 , wherein the feedback circuit comprises:
a current digital-to-analog converter configured to generate a first feedback current according to the first digital code;
a first voltage-controlled current source (VCCS) group configured to generate a second feedback current according to the first quantization error signal; and
a second VCCS group configured to generate a third feedback current according to the second quantization error signal.
8. The CT-DSM of claim 7 , wherein the first VCCS group or the second VCCS group comprises:
a first VCCS sub-group configured to generate a first current according to the first quantization error signal or the second quantization error signal;
a second VCCS sub-group configured to generate a second current according to the first quantization error signal or the second quantization error signal; and
a third VCCS sub-group configured to generate a third current according to the first quantization error signal or the second quantization error signal;
wherein the second feedback current or the third feedback current includes the first current, the second current, and the third current, the first current is inputted to the loop filter, and the second current and the third current are inputted to the ELD compensation circuit.
9. The CT-DSM of claim 8 , wherein the second VCCS sub-group comprises a plurality of VCCSs, and each VCCS has an input terminal and an output terminal and comprises:
a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the first terminal is coupled to a first reference voltage;
a second transistor having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is coupled to a second reference voltage, and the second control terminal is coupled to a third reference voltage;
a capacitor having a fifth terminal and a sixth terminal;
a first switch coupled between the fifth terminal and a fourth reference voltage;
a second switch coupled between the fifth terminal and a fifth reference voltage;
a third switch coupled between the sixth terminal and the input terminal;
a fourth switch coupled between the sixth terminal and the first control terminal;
a fifth switch coupled between the fourth reference voltage and the first control terminal;
a sixth switch coupled between the fourth terminal and the output terminal; and
a seventh switch coupled between the second terminal and the output terminal.
10. The CT-DSM of claim 9 , wherein the second switch and the third switch are turned on simultaneously, the first switch and the fourth switch are turned on simultaneously, and the sixth switch and the seventh switch are turned on simultaneously.