Granted Patent B2

US 12,408,316 · App. 18/756,363 · Granted Sep 2, 2025

Inventors: Hidehiro Fujiwara (Hsinchu, TW); Chih-Yu Lin (Hsinchu, TW); Hsien-Yu Pan (Hsinchu, TW); Yasutoshi Okuno (Hsinchu, TW); Yen-Huei Chen (Hsinchu, TW); Hung-Jen Liao (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H10B10/12G06F30/392H01L23/5226H01L23/5286H10D89/10

Abstract

Claims (82)

1. A memory cell comprising:

a first pull up transistor;

a first pass gate transistor coupled to the first pull up transistor;

a second pull up transistor having a first active region extending in a first direction, and the first active region being located on a first level;

a second pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction, and the second active region being adjacent to the first active region, the second pass gate transistor being coupled to the second pull up transistor; and

a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the second pull up transistor to a drain of the second pass gate transistor;

wherein the first pass gate transistor, the second pass gate transistor, the first pull up transistor and the second pull up transistor are part of a four transistor (4T) memory cell.

2. The memory cell of claim 1 , further comprising:

a second metal contact extending in the second direction, overlapping the first active region, and being located on the second level, the second metal contact being electrically coupled to a source of the second pull down transistor and a voltage supply; and

a third metal contact extending in the second direction, overlapping the second active region, and being located on the second level, the third metal contact being electrically coupled to a source of the second pass gate transistor.

3. The memory cell of claim 2 , further comprising:

a set of gates comprising:

a first gate extending in the second direction, overlapping the first active region, and being located on the second level; and

a second gate extending in the second direction, overlapping the second active region being located on the second level, and being separated from the first gate in the second direction.

4. The memory cell of claim 3 , further comprising:

a first set of conductive structures extending in the first direction and overlapping at least the first active region, the second active region or the set of gates, each conductive structure of the first set of conductive structures being separated from an adjacent conductive structure of the first set of conductive structures in at least the first direction or the second direction, and being located on a third level different from the first level and the second level.

5. The memory cell of claim 4 , further comprising:

a first set of vias between the first set of conductive structures and the first active region and the second active region, the first set of vias coupling the first set of conductive structures to at least the first active region, the second active region or the set of gates, and at least one via of the first set of vias being located where at least one conductive structure of the first set of conductive structures overlaps at least one of the first active region, the second active region or the set of gates.

6. The memory cell of claim 5 , further comprising:

a second set of conductive structures extending in the second direction and overlapping at least the first active region, the second active region or the first set of conductive structures, each conductive structure of the second set of conductive structures being separated from an adjacent structure of the second set of conductive structures in the first direction, and being located on a fourth level different from the first level, the second level and the third level; and

a second set of vias between the second set of conductive structures and the first set of conductive structures, the second set of vias coupling the second set of conductive structures to the first set of conductive structures, and at least one via of the second set of vias being located where at least one conductive structure of the second set of conductive structures overlaps at least one of the first set of conductive structures.

7. The memory cell of claim 6 , further comprising:

a third set of conductive structures extending in the first direction and overlapping at least the second set of conductive structures, each conductive structure of the third set of conductive structures being separated from an adjacent structure of the third set of conductive structures in the second direction, and being located on a fifth level different from the first level, the second level, the third level and the fourth level; and

a third set of vias between the third set of conductive structures and the second set of conductive structures, the third set of vias coupling the third set of conductive structures to the second set of conductive structures, and at least one via of the third set of vias being located where at least one conductive structure of the third set of conductive structures overlaps at least one conductive structure of the second set of conductive structures.

8. A memory cell comprising:

a first pull down transistor having a first active region extending in a first direction, and the first active region being located on a first level;

a first pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction;

a second pull down transistor having a third active region extending in the first direction, the third active region being located on the first level, and being separated from the first active region in the first direction;

a second pass gate transistor having a fourth active region extending in the first direction, the fourth active region being located on the first level, being separated from the third active region in the second direction, and being separated from the second active region in the first direction; and

a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the first pull down transistor to a drain of the first pass gate transistor,

wherein the first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

9. The memory cell of claim 8 , further comprising:

a set of gates comprising:

a first gate extending in the second direction, overlapping the first active region or the second active region, and being located on the second level; and

a second gate extending in the second direction, overlapping the third active region or the fourth active region, being located on the second level, and being separated from the first gate in the second direction.

10. The memory cell of claim 9 , further comprising:

a first set of conductive structures extending in the first direction and overlapping at least the first active region, the second active region, the third active region, the fourth active region or the set of gates, each conductive structure of the first set of conductive structures being separated from an adjacent conductive structure of the first set of conductive structures in at least the first direction or the second direction, and being located on a third level different from the first level and the second level; and

a first set of vias between the first set of conductive structures and the first active region and the second active region, the first set of vias coupling the first set of conductive structures to at least the first active region, the second active region, the third active region, the fourth active region or the set of gates, and at least one via of the first set of vias being located where at least one conductive structure of the first set of conductive structures overlaps at least one of the first active region or the second active region.

11. The memory cell of claim 10 , further comprising:

a second set of conductive structures extending in the second direction and overlapping at least the first active region, the second active region, the third active region, the fourth active region or the first set of conductive structures, each conductive structure of the second set of conductive structures being separated from an adjacent structure of the second set of conductive structures in the first direction, and being located on a fourth level different from the first level, the second level and the third level; and

a second set of vias between the second set of conductive structures and the first set of conductive structures, the second set of vias coupling the second set of conductive structures to the first set of conductive structures, and at least one via of the second set of vias being located where at least one conductive structure of the second set of conductive structures overlaps at least one of the first set of conductive structures.

12. The memory cell of claim 11 , further comprising:

a third set of conductive structures extending in the first direction and overlapping at least the second set of conductive structures, each conductive structure of the third set of conductive structures being separated from an adjacent structure of the third set of conductive structures in the second direction, and being located on a fifth level different from the first level, the second level, the third level and the fourth level; and

a third set of vias between the third set of conductive structures and the second set of conductive structures, the third set of vias coupling the third set of conductive structures to the second set of conductive structures, and at least one via of the third set of vias being located where at least one conductive structure of the third set of conductive structures overlaps at least one conductive structure of the second set of conductive structures.

13. The memory cell of claim 12 , wherein

the first set of vias comprises:

a first via of the first set of vias electrically coupling the first gate to a first conductive structure of the first set of conductive structures; and

a second via of the first set of vias electrically coupling the second gate to the first conductive structure of the first set of conductive structures;

the second set of vias comprises:

a first via of the second set of vias electrically coupling the first conductive structure of the first set of conductive structures to a first conductive structure of the second set of conductive structures; and

a second via of the second set of vias electrically coupling the first conductive structure of the first set of conductive structures to a second conductive structure of the second set of conductive structures; and

the third set of vias comprises:

a first via of the third set of vias electrically coupling a first conductive structure of the third set of conductive structures to a third conductive structure of the second set of conductive structures, the first conductive structure of the third set of conductive structures corresponding to a power supply rail coupled to a voltage supply or a reference supply.

14. A memory cell comprising:

a first pull down transistor;

a first pass gate transistor coupled to the first pull down transistor;

a second pull down transistor having a first active region extending in a first direction, and the first active region being located on a first level;

a second pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction, the second pass gate transistor coupled to the second pull down transistor;

a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor; and

wherein the first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

15. The memory cell of claim 14 , further comprising:

a second metal contact extending in the second direction, overlapping the first active region, and being located on the second level, the second metal contact being electrically coupled to a source of the second pull down transistor and a reference voltage supply; and

a third metal contact extending in the second direction, overlapping the second active region, and being located on the second level, the third metal contact being electrically coupled to a source of the second pass gate transistor.

16. The memory cell of claim 15 , further comprising:

a set of gates comprising:

a first gate extending in the second direction, overlapping the first active region, and being located on the second level; and

a second gate extending in the second direction, overlapping the second active region being located on the second level, and being separated from the first gate in the second direction.

17. The memory cell of claim 16 , further comprising:

a first set of conductive structures extending in the first direction and overlapping at least the first active region, the second active region or the set of gates, each conductive structure of the first set of conductive structures being separated from an adjacent conductive structure of the first set of conductive structures in at least the first direction or the second direction, and being located on a third level different from the first level and the second level; and

a first set of vias between the first set of conductive structures and at least the first active region, the second active region or the set of gates, the first set of vias coupling the first set of conductive structures to at least the first active region, the second active region or the set of gates, and at least one via of the first set of vias being located where at least one conductive structure of the first set of conductive structures overlaps at least one of the first active region, the second active region or the set of gates.

18. The memory cell of claim 17 , further comprising:

a second set of conductive structures extending in the second direction and overlapping at least the first active region, the second active region or the first set of conductive structures, each conductive structure of the second set of conductive structures being separated from an adjacent structure of the second set of conductive structures in the first direction, and being located on a fourth level different from the first level, the second level and the third level; and

a second set of vias between the second set of conductive structures and the first set of conductive structures, the second set of vias coupling the second set of conductive structures to the first set of conductive structures, and at least one via of the second set of vias being located where at least one conductive structure of the second set of conductive structures overlaps at least one of the first set of conductive structures.

19. The memory cell of claim 18 , further comprising:

a third set of conductive structures extending in the first direction and overlapping at least the second set of conductive structures, each conductive structure of the third set of conductive structures being separated from an adjacent structure of the third set of conductive structures in the second direction, and being located on a fifth level different from the first level, the second level, the third level and the fourth level; and

a third set of vias between the third set of conductive structures and the second set of conductive structures, the third set of vias coupling the third set of conductive structures to the second set of conductive structures, and at least one via of the third set of vias being located where at least one conductive structure of the third set of conductive structures overlaps at least one conductive structure of the second set of conductive structures.

20. The memory cell of claim 19 , wherein

the first set of vias comprises:

a first via of the first set of vias electrically coupling the first gate to a first conductive structure of the first set of conductive structures; and

a second via of the first set of vias electrically coupling the second gate to a second conductive structure of the first set of conductive structures; and

the second set of vias comprises:

a first via of the second set of vias electrically coupling the second conductive structure of the first set of conductive structures to a first conductive structure of the second set of conductive structures, the first conductive structure of the second set of conductive structures corresponding to a first word line.

Assignments (1)

Continuity (5)

References Cited (14)