Field-effect transistors with heterogenous doped regions in the substrate of a silicon-on-insulator substrate
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate. The semiconductor substrate includes first and second doped regions, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. The structure further comprises first and second source/drain regions in the semiconductor layer, and a gate structure laterally between the first source/drain region and the second source/drain region. The first source/drain region overlaps with the first doped region, and the second source/drain region overlaps with the second doped region.
1. A structure comprising:
a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate, the semiconductor substrate including a first doped region and a second doped region, the first doped region having a first conductivity type, and the second doped region having a second conductivity type different from the first conductivity type;
a first source/drain region in the semiconductor layer, the first source/drain region overlapping with the first doped region;
a second source/drain region in the semiconductor layer, the second source/drain region overlapping with the second doped region; and
a first gate structure laterally between the first source/drain region and the second source/drain region,
wherein the semiconductor substrate includes a third doped region having the second conductivity type, the first doped region is laterally positioned between the second doped region and the third doped region, the first gate structure has a width, and the second doped region is laterally spaced from the third doped region by a distance greater than two times the width of the first gate structure.
2. The structure of claim 1 further comprising:
a second gate structure,
wherein the first source/drain region is positioned laterally between the first gate structure and the second gate structure.
3. The structure of claim 2 wherein the first gate structure and the second gate structure overlap with the first doped region.
4. The structure of claim 2 wherein the first doped region and the second doped region adjoin along an interface, and the first gate structure is aligned with the interface.
5. The structure of claim 2 wherein the first doped region and the second doped region adjoin along an interface, and the first gate structure is non-aligned with the interface.
6. The structure of claim 2 further comprising:
a third gate structure,
wherein the second source/drain region is positioned laterally between the first gate structure and the third gate structure.
7. The structure of claim 6 wherein the third gate structure overlaps with the second doped region.
8. The structure of claim 6 where the first source/drain region is a drain terminal, and the second source/drain region is a source terminal.
9. The structure of claim 1 where the first source/drain region is a drain terminal, and the second source/drain region is a source terminal.
10. The structure of claim 1 wherein the silicon-on-insulator substrate includes an active region and a hybrid region, the first source/drain region and the second source/drain region are positioned in the active region, and further comprising:
a well in the hybrid region of the semiconductor substrate,
wherein the well has the second conductivity type, and the second doped region is coupled to the well.
11. The structure of claim 10 wherein the first conductivity type is p-type, and the second conductivity type is n-type.
12. The structure of claim 1 further comprising:
a third source/drain region in the semiconductor layer, the third source/drain region overlapping with the third doped region.
13. The structure of claim 12 wherein the first source/drain region is a drain terminal, and the second source/drain region and the third source/drain region are source terminals.
14. The structure of claim 12 wherein the first source/drain region and the third source/drain region are input/output terminals.
15. The structure of claim 1 wherein the dielectric layer has a thickness in a range of about 4 nanometers to about 40 nanometers.
16. The structure of claim 1 wherein the semiconductor layer has a first side edge and a second side edge, and the second doped region extends in the semiconductor substrate from the first side edge of the semiconductor layer to the second side edge of the semiconductor layer.
17. The structure of claim 16 wherein the silicon-on-insulator substrate includes an active region and a hybrid region, the first source/drain region and the second source/drain region are positioned in the active region, and the second doped region extends outwardly beyond the first side edge and the second side edge into the hybrid region.
18. The structure of claim 17 further comprising:
a well in the hybrid region of the semiconductor substrate,
wherein the well has the second conductivity type, and the second doped region is coupled to the well.
19. The structure of claim 17 wherein the third doped region extends in the semiconductor substrate from the first side edge of the semiconductor layer to the second side edge of the semiconductor layer, and the third doped region extends outwardly beyond the first side edge and the second side edge into the hybrid region.
20. A method comprising:
forming a first doped region and a second doped region in a semiconductor substrate of a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate includes a semiconductor layer and a dielectric layer between the semiconductor layer and the semiconductor substrate, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type;
forming a first source/drain region in the semiconductor layer, wherein the first source/drain region overlaps with the first doped region;
forming a second source/drain region in the semiconductor layer, wherein the second source/drain region overlaps with the second doped region; and
forming a gate structure laterally between the first source/drain region and the second source/drain region,
wherein the semiconductor substrate includes a third doped region having the second conductivity type, the first doped region is laterally positioned between the second doped region and the third doped region, the gate structure has a width, and the second doped region is laterally spaced from the third doped region by a distance greater than two times the width of the gate structure.