Transistor element including a buried insulating layer having enhanced functionality
In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
1. A transistor element, comprising
a channel region formed in a semiconductor layer and being laterally positioned between a drain region and a source region;
a control gate electrode structure formed on said channel region;
a buried insulating layer stack formed below said semiconductor layer and comprising at least two different dielectric material layers; and
a semiconductor body region formed below said buried insulating layer stack and being connected for receiving a control voltage, wherein said semiconductor body region comprises first and second doped regions, said second doped region is of inverse conductivity type compared to said first doped region, a first portion of said first doped region and a second portion of said second doped region directly contact said buried insulating layer stack, said first and second portions are disposed vertically below and overlapping said control gate electrode structure when viewed from above said control gate electrode structure, and said first portion is disposed vertically below and overlapping one of said source region or said drain region, and said second portion is disposed vertically below and overlapping the other of said source region or said drain region.
2. The transistor element of claim 1 , wherein said buried insulating layer stack comprises a charge trapping layer.
3. The transistor element of claim 2 , wherein said charge trapping layer comprises at least one of nitrogen and hafnium.
4. The transistor element of claim 2 , wherein said buried insulating layer stack further comprises a blocking dielectric layer formed so as to separate said charge trapping layer from said semiconductor layer.
5. The transistor element of claim 2 , wherein said buried insulating layer stack further comprises a charge tunneling layer formed so as to enable charge carrier tunneling therethrough and separate said charge trapping layer from said semiconductor body region.
6. The transistor element of claim 1 , wherein said buried insulating layer stack comprises at least one high-k dielectric layer that comprises a high-k dielectric material having a permittivity of at least 20.
7. The transistor element of claim 6 , wherein said buried insulating layer stack further comprises two or more non-high-k dielectric layers that comprise a dielectric material having a dielectric constant of 10 or less.
8. The transistor element of claim 6 , wherein a thickness of said at least one high-k dielectric layer is greater than a thickness of any non-high-k dielectric layer of said buried insulating layer stack.
9. The transistor element of claim 8 , wherein a thickness of said at least one high-k dielectric layer is greater than a combined thickness of all non-high-k dielectric layers of said buried insulating layer stack.
10. The transistor element of claim 1 , wherein said buried insulating layer stack comprises a ferroelectric layer having a configuration so as to enable establishing a polarization that is oriented substantially perpendicular to a current flow direction in said channel region.
11. The transistor element of claim 10 , wherein said buried insulating layer stack further comprises a non-ferroelectric dielectric layer formed so as to separate said ferroelectric layer from said semiconductor layer.
12. A transistor element, comprising:
a channel region formed in a semiconductor layer and being laterally positioned between a drain region and a source region;
a control gate electrode structure formed on said channel region;
a buried insulating layer formed below said semiconductor layer and comprising a charge trapping material; and
a semiconductor body region formed below said buried insulating layer and being connected for receiving a control voltage, wherein said semiconductor body region comprises first and second doped regions for adjusting a type of charge carriers to be trapped in said charge trapping layer, said second doped region is of inverse conductivity type compared to said first doped region, a first portion of said first doped region and a second portion of said second doped region directly contact said buried insulating layer, said first and second portions are disposed vertically below and overlapping said control gate electrode structure when viewed from above said control gate electrode structure, and said first portion is disposed vertically below and overlapping one of said source region or said drain region, and said second portion is disposed vertically below and overlapping the other of said source region or said drain region.
13. The transistor element of claim 12 , further comprising a buffer dielectric layer formed above said charge trapping material so as to separate said charge trapping material from said semiconductor layer.
14. The transistor element of claim 13 , further comprising a further dielectric layer formed below said charge trapping material so as to separate said charge trapping material from said semiconductor body region.
15. The transistor element of claim 12 , wherein said charge trapping material comprises at least one of nitrogen and hafnium.
16. A transistor element, comprising:
a channel region formed in a semiconductor layer and being laterally positioned between a drain region and a source region;
a control gate electrode structure formed on said channel region;
a buried insulating layer formed below said semiconductor layer and comprising a high-k dielectric material; and
a semiconductor body region formed below said buried insulating layer and being connected for receiving a control voltage, wherein said semiconductor body region comprises first and second doped regions, said second doped region is of inverse conductivity type compared to said first doped region, a first portion of said first doped region and a second portion of said second doped region directly contact said buried insulating layer, said first and second portions are disposed vertically below and overlapping said control gate electrode structure when viewed from above said control gate electrode structure, and said first portion is disposed vertically below and overlapping one of said source region or said drain region, and said second portion is disposed vertically below and overlapping the other of said source region or said drain region.
17. The transistor element of claim 16 , wherein said high-k dielectric material comprises a dielectric material having a permittivity of 20 or higher.
18. The transistor element of claim 17 , further comprising at least one non-high-k dielectric layer separating said high-k dielectric material from said semiconductor layer.