IP Library Granted Patent US 12,411,470
Granted Patent B2
US 12,411,470 · App. 17/919,344 · Granted Sep 9, 2025

Control system performance tracking apparatus and method

Inventors: Philip Colin Chandler (Bristol, GB); Darren Mark Brown (Gloucestershire, GB); Michael Sean Finney (Bristol, GB)
Assignee: DATUMPIN LTD
G05B19/058G05B2219/14006
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Quick Facts
Patent No.
US 12,411,470
App. No.
17/919,344
Granted
Sep 9, 2025
Kind
B2
Abstract

The present invention relates to a control system performance tracking apparatus comprising: a data memory device coupled in use to a plurality of control devices of a control system, the data memory device being configured to: monitor the plurality of control devices; receiving data related to inputs, outputs and events of each control device; time stamp said data on a common time base; and store a resulting time-based sequence data for each of the plurality of control devices; and a processor configured to compile the sequence data for the plurality of control devices into a common data stack.

Claims (58)

1. A control system performance tracking apparatus comprising:

a data memory device coupled in use to a plurality of control devices of a control system, the data memory device being configured to:

monitor the plurality of control devices;

receiving data related to inputs, outputs and events of each control device;

time stamp said data on a common time base; and

store a resulting time-based sequence data for each of the plurality of control devices; and

a processor configured to compile the sequence data for the plurality of control devices into a common data stack

wherein the apparatus is further configured to:

accumulate historical data to form at least one reference sequence data model; and

compare a measured sequence data to the reference sequence data model to identify operational deviations,

wherein the data memory device compiles at least the following groups of device data:

Digital Input/Output data, Analogue Input/Output data and event logs and the reference sequence data model comprises Digital Input/Output data to provide reference sequence data models for sub-processes.

2. The performance tracking apparatus of claim 1 , wherein the apparatus further comprises a playback method to enable a user to search and/or replay the data stack.

3. The performance tracking apparatus of claim 1 , the processor is further configured to use the data stack to provide predicted future control system behaviour.

4. The performance tracking apparatus of claim 1 , wherein the reference sequence data model is a data-stack model and the measured sequence data compares the measured data-stack to the data stack model.

5. The performance tracking apparatus of claim 1 , wherein at least one of the plurality of control devices is a Programmable Logic Controller (PLC) device,

the PLC device comprising: an input module to receive inputs from at least one input source; a processor configured to process said inputs according to a control logic stored on a machine readable memory of the processor to provide outputs; and an output module to issue said outputs to a connected device;

and wherein the data memory device being embedded to and interfaced with the PLC device.

6. The performance tracking apparatus of claim 5 , wherein the events of the PLC device include messages provided by the processor to a Human Machine Interface (HMI) and/or to a Supervisory, Control and Data Acquisition (SCDA) interface.

7. The performance tracking apparatus of claim 6 , wherein the apparatus combines outputs from a plurality of SCADA systems.

8. The performance tracking apparatus of claim 1 , wherein the data memory device comprises:

an input interface for receiving data from the plurality of control devices;

a clock;

a processor configured to timestamp said received data; and

a machine-readable data storage; and

an output interface.

9. The performance tracking apparatus of claim 8 , wherein the input interface comprises a unidirectional gateway firewall.

10. The performance tracking apparatus of claim 8 , wherein the reference sequence model comprises Analogue Input/Output and comparing measured sequence data comprises comparing data topology.

11. The performance tracking apparatus of claim 8 wherein the data memory device is further configured to cross-reference time-stamped event log data as way points in the sequence data.

12. The performance tracking apparatus of claim 8 , further comprising a monitoring device configured to monitor the Sequence data from the data memory device and issue an alert or notification based upon deviations from the reference sequence model.

13. A control system performance tracking apparatus comprising:

a data memory device coupled in use to a plurality of control devices of a control system, the data memory device being configured to:

monitor the plurality of control devices;

receiving data related to inputs, outputs and events of each control device;

time stamp said data on a common time base; and

store a resulting time-based sequence data for each of the plurality of control devices; and

a processor configured to compile the sequence data for the plurality of control devices into a common data stack

wherein the data memory device comprises:

an input interface for receiving data from the plurality of control devices;

a clock;

a processor configured to timestamp said received data; and

a machine-readable data storage; and

an output interface

wherein the apparatus is further configured to:

accumulate historical data to form at least one reference sequence data model; and

compare a measured sequence data to the reference sequence data model to identify operational deviations, and

wherein the reference sequence model comprises Analogue Input/Output and comparing measured sequence data comprises comparing data topology.

14. A control system performance tracking apparatus comprising:

a data memory device coupled in use to a plurality of control devices of a control system, the data memory device being configured to:

monitor the plurality of control devices;

receiving data related to inputs, outputs and events of each control device;

time stamp said data on a common time base; and

store a resulting time-based sequence data for each of the plurality of control devices; and

a processor configured to compile the sequence data for the plurality of control devices into a common data stack

wherein the apparatus is further configured to:

accumulate historical data to form at least one reference sequence data model; and

compare a measured sequence data to the reference sequence data model to identify operational deviations, and

wherein the data memory device is further configured to cross-reference time-stamped event log data as way points in the sequence data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2022
From: CHANDLER, PHILIP COLIN; BROWN, DARREN MARK; FINNEY, MICHAEL SEAN
To: DATUMPIN LTD
Reel/Frame 061967/0709 →
Priority Claims (1)
GB 2006981 · May 12, 2020 · national
Continuity (1)
Related Publication 20230161313A1 · May 25, 2023
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