IP Library › Granted Patent US 12,411,692
Granted Patent B2
US 12,411,692 · App. 18/462,742 · Granted Sep 9, 2025

Storage of prediction-related data

Inventors: Houdhaifa Bouzguarrou (Austin, TX); Alexander Cole Shulyak (Austin, TX); Rami Mohammad Al Sheikh (Morrisville, NC)
Assignee: Arm Limited
G06F9/321G06F9/30058G06F9/325G06F9/3844
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Quick Facts
Patent No.
US 12,411,692
App. No.
18/462,742
Granted
Sep 9, 2025
Kind
B2
Abstract

A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.

Claims (54)

1. A data processing apparatus comprising:

pointer storage configured to store pointer values for a plurality of pointers;

increment circuitry, responsive to one or more increment events, to increment each of the pointer values in dependence on a corresponding live pointer value update condition from a plurality of corresponding live pointer value update conditions, wherein the corresponding live pointer value update condition is different for each of the pointers; and

history storage circuitry configured to store resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers, wherein

at least one of the live pointer value update conditions is changeable at runtime.

2. The data processing apparatus according to claim 1 , wherein

at least one other of the live pointer value update conditions is immutable at runtime.

3. The data processing apparatus according to claim 1 , wherein

the at least one of the live pointer value update conditions is based on a program counter value.

4. The data processing apparatus according claim 3 , wherein

the at least one of the live pointer value update conditions is based on the current program counter value matching a corresponding pattern.

5. The data processing apparatus according to claim 4 , wherein

the at least one of the live pointer value update conditions is changed by changing the corresponding pattern.

6. The data processing apparatus according to claim 1 , wherein

the one or more increment events comprise a backwards taken branch.

7. The data processing apparatus according to claim 1 , wherein

the live pointer value update condition is based on a type of the backwards taken branch.

8. The data processing apparatus according to claim 1 , comprising:

counter storage circuitry configured to store confidence values, each of the confidence values corresponding with one of the live pointer value update conditions, wherein

each of the at least some of the live pointer value update conditions are changed in dependence on its corresponding confidence value.

9. The data processing apparatus according to claim 8 , wherein

each of the at least some of the live pointer value update conditions are changed in dependence on its corresponding confidence value being less than a predetermined limit after a predetermined period.

10. The data processing apparatus according to claim 8 , wherein

each of the at least some of the live pointer value update conditions are changed as a consequence of being in a smallest N of the confidence values stored in the counter storage circuitry.

11. The data processing apparatus according to claim 8 , comprising:

prediction circuitry, responsive to a prediction trigger associated with a replay of a given instance of a given control flow instruction, to select a subset of resolved behaviour associated with one of the pointer values to make a prediction of a given instance of the given control flow instruction.

12. The data processing apparatus according to claim 11 , comprising:

training circuitry configured, in response to the subset of resolved behaviour being used to make the prediction, to increment its corresponding confidence value.

13. The data processing apparatus according to claim 1 , wherein

the live pointer value update conditions and at least one suspended pointer value update conditions form a superset of available pointer value update conditions; and

the at least one of the live pointer value update conditions is changeable to one of the at least one suspended pointer value update conditions.

14. The data processing apparatus according to claim 1 , comprising:

recovery circuitry configured to recover a previous value of the pointer values for each of the live pointer value update conditions, wherein

the history storage circuitry is configured to store the previous value of the pointer values for each of the live pointer value update conditions.

15. The data processing apparatus according to claim 1 , comprising:

inference circuitry configured to infer an inferred pointer value from an inferring pointer value corresponding to one of the live pointer value update conditions.

16. The data processing apparatus according to claim 15 , wherein

the inferred pointer value corresponds with one of the pointer value update conditions that is an inverse of the one of the active pointer update conditions.

17. A system comprising:

the data processing apparatus of claim 1 , implemented in at least one packaged chip;

at least one system component; and

a board, wherein

the at least one packaged chip and the at least one system component are assembled on the board.

18. A chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component.

19. A data processing method comprising:

storing pointer values for a plurality of pointers;

responding to one or more increment events by incrementing each of the pointer values in dependence on a corresponding live pointer value update condition from a plurality of corresponding live pointer value update conditions, wherein the corresponding live pointer value update condition is different for each of the pointers; and

storing resolved behaviours of instances of a control flow instruction, each of the sets being associated with one of the pointers, wherein

at least one of the live pointer value update conditions is changeable at runtime.

20. A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising:

pointer storage configured to store pointer values for a plurality of pointers;

increment circuitry, responsive to one or more increment events, to increment each of the pointer values in dependence on a corresponding live pointer value update condition from a plurality of corresponding live pointer value update conditions, wherein the corresponding live pointer value update condition is different for each of the pointers; and

history storage circuitry configured to store resolved behaviours of instances of a control flow instruction, each of the sets being associated with one of the pointers, wherein

at least one of the live pointer value update conditions is changeable at runtime.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2023
From: BOUZGUARROU, HOUDHAIFA; SHULYAK, ALEXANDER COLE; AL SHEIKH, RAMI MOHAMMAD
To: ARM LIMITED
Reel/Frame 065532/0651 →
Continuity (1)
Related Publication 20250085971A1 · Mar 13, 2025
References Cited (38)
US 6006317A · Ramagopal et al. · 1999 [cited by applicant]
US 6385720B1 · Tanaka · 2002 [cited by examiner]
US 6694425B1 · Eickemeyer · 2004 [cited by applicant]
US 8078852B2 · Al-Otoom · 2011 [cited by examiner]
US 8751776B2 · Ukai · 2014 [cited by applicant]
US 9639368B2 · Bonanno · 2017 [cited by examiner]
US 9891918B2 · Hooker et al. · 2018 [cited by applicant]
US 9973187B1 · Pant et al. · 2018 [cited by applicant]
US 10223123B1 · Blasco et al. · 2019 [cited by applicant]
US 10846097B2 · Jumani et al. · 2020 [cited by applicant]
US 10915322B2 · Annamalai · 2021 [cited by examiner]
US 11334361B2 · Ishii et al. · 2022 [cited by applicant]
US 11983533B2 · Pusdesris · 2024 [cited by examiner]
US 20040255104A1 · Akkary et al. · 2004 [cited by applicant]
US 20050138480A1 · Srinivasan et al. · 2005 [cited by applicant]
US 20110238917A1 · Lin · 2011 [cited by applicant]
US 20160092230A1 · Chen · 2016 [cited by applicant]
US 20160350116A1 · Reddy et al. · 2016 [cited by applicant]
US 20170010820A1 · Day · 2017 [cited by applicant]
US 20180088953A1 · Lin · 2018 [cited by applicant]
US 20200050459A1 · Palivela · 2020 [cited by applicant]
US 20200104137A1 · Natarajan · 2020 [cited by applicant]
US 20200174794A1 · Golla · 2020 [cited by applicant]
US 20210081575A1 · Saileshwar · 2021 [cited by applicant]
US 20210124586A1 · Bouzguarrou · 2021 [cited by applicant]
US 20210240476A1 · Kountanis · 2021 [cited by applicant]
US 20220197650A1 · Soundararajan · 2022 [cited by applicant]
US 20230057600A1 · Malley · 2023 [cited by applicant]
U.S. Appl. No. 17/851,266, filed Jun. 28, 2022, Shulyak et al. [cited by applicant]
U.S. Appl. No. 18/312,052, filed May 4, 2023, Shulyak et al. [cited by applicant]
U.S. Appl. No. 18/454,158, filed Aug. 23, 2023, Bouzguarrou et al. [cited by applicant]
U.S. Appl. No. 18/454,165, filed Aug. 23, 2023, Bouzguarrou et al. [cited by applicant]
Office Action dated Aug. 9, 2023 for U.S. Appl. No. 17/851,266, 11 pages. [cited by applicant]
Akkary, H. et al. “Recycling Waste: Exploiting Wrong-Path Execution to Improve Branch Prediction” ICS'03, Jun. 23-26, 2003, pp. 12-21 (10 pages). [cited by applicant]
Mutlu, O. et al. “On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor” IEEE Computer Architecture Letters, 2005, vol. 4 (4 pages). [cited by applicant]
Notice of Allowance dated Aug. 22, 2024 for U.S. Appl. No. 18/312,052, 15 pages. [cited by applicant]
Office Action dated May 6, 2025 for U.S. Appl. No. 18/454,165, 19 pages. [cited by applicant]
Zi-Chao Xie et al., “SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers” Journal of Computer Science and Technology, vol. 27, No. 4, Jul. 2012, pp. 754-768. [cited by applicant]