Semiconductor device with power via
A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.
1. A semiconductor device comprising:
a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
a dielectric liner and a dielectric core formed in the gate cut region;
a backside power rail (BPR) and a backside power distribution network (BSPDN);
a power via passing through the dielectric core and connecting to the BPR and the BSPDN;
first metal contacts formed in contact with the first and second S/D epitaxial regions; and
a via to backside power rail (VBPR) contact,
wherein the dielectric liner separates the power via from the first S/D epitaxial region, and a portion of the dielectric liner is removed on only one side of the power via and the VBPR contact is formed in a location where this portion of the dielectric liner is removed.
2. The semiconductor device of claim 1 , wherein the VBPR contact connects the second S/D epitaxial region with the power via and the first metal contact that is in contact with the second S/D epitaxial region.
3. The semiconductor device of claim 1 , wherein a portion of the dielectric core is removed and the power via is formed in a location where this portion of the dielectric core is removed.
4. The semiconductor device of claim 1 , further comprising a BOX layer between the first and second S/D epitaxial regions.
5. The semiconductor device according to claim 4 , wherein the power via extends through the BOX layer to contact the BPR.
6. The semiconductor device according to claim 1 , wherein the dielectric liner separates the power via from the first S/D epitaxial region.
7. The semiconductor device according to claim 1 , wherein the first and second S/D epitaxial regions comprise one of a p-type and an n-type material.
8. The semiconductor device according to claim 1 , further comprising third and fourth S/D epitaxial regions.
9. The semiconductor device according to claim 1 , further comprising a BEOL connected to the first metal contacts.
10. A method of manufacturing a semiconductor device, the method comprising:
forming a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
forming a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
forming a dielectric liner and a dielectric core in the gate cut region;
forming a backside power rail (BPR) and a backside power distribution network (BSPDN);
forming a power via passing through the dielectric core and connecting to the BPR and BSPDN;
forming first metal contacts in contact with the first and second S/D epitaxial regions; and
forming a via to backside power rail (VBPR) contact,
wherein the dielectric liner separates the power via from the first S/D epitaxial region, and a portion of the dielectric liner is removed on only one side of the power via and the VBPR contact is formed in a location where this portion of the dielectric liner is removed.
11. The method of claim 10 , wherein the VBPR contact connects the second S/D epitaxial region with the power via and the first metal contact that is in contact with the second S/D epitaxial region.
12. The method of claim 10 , wherein a portion of the dielectric core is removed and the power via is formed in a location where this portion of the dielectric core is removed.
13. The method of claim 10 , further comprising forming a BOX layer between the first and second S/D epitaxial regions.
14. The method according to claim 13 , wherein the power via extends through the BOX layer to contact the BPR.
15. The method according to claim 10 , wherein the dielectric liner separates the power via from the first S/D epitaxial region.
16. The method according to claim 10 , wherein the first and second S/D epitaxial regions comprise one of a p-type and an n-type material.
17. The method according to claim 10 , further comprising forming third and fourth S/D epitaxial regions.
18. A semiconductor device comprising:
a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
a first dielectric fill layer and a second dielectric fill layer formed in the gate cut region; and
a backside power rail (BPR) connected to a backside power distribution network (BSPDN),
wherein a portion of the second first dielectric fill layer is removed on only one side of the gate cut region and replaced with a power bar, which connects at least one of the first and second S/D epitaxial regions to the backside power rail.