IP Library › Granted Patent US 12,413,152
Granted Patent B2
US 12,413,152 · App. 18/455,417 · Granted Sep 9, 2025

Switching control circuit and power supply circuit

Inventors: Hiroaki Matsumoto (Matsumoto, JP); Jun Asai (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H02M3/33569H02M1/0035H02M3/01
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,413,152
App. No.
18/455,417
Granted
Sep 9, 2025
Kind
B2
Abstract

A switching control circuit for a power supply circuit that includes a transformer including primary and secondary coils, and first and second transistors controlling a current flowing through the primary coil. The power supply circuit generates an output voltage at a target level. The switching control circuit controls switching of the first and second transistors. The switching control circuit includes: a drive signal output circuit configured to output drive signals according to a normal mode, when the output voltage is lower than a first level, and output the drive signals according to a burst mode, when the output voltage is higher than the first level; and a driver circuit configured to switch the first and second transistors in response to the drive signals. The drive signal output circuit reduces a first time period in the burst mode, in response to the output voltage rising above the first level.

Claims (40)

1. A switching control circuit for a power supply circuit that includes

a transformer including a primary coil and a secondary coil, and

first and second transistors configured to control a current flowing through the primary coil,

the power supply circuit being configured to generate an output voltage at a target level, the switching control circuit configured to control switching of the first and second transistors, the switching control circuit comprising:

a drive signal output circuit configured to

output drive signals according to a normal mode, when the output voltage is lower than a first level, and

output the drive signals according to a first burst mode, when the output voltage is higher than the first level; and

a driver circuit configured to switch the first and second transistors in response to the drive signals, wherein

the normal mode is a mode in which the first and second transistors are continuously switched, in a first cycle based on a feedback voltage corresponding to the output voltage,

the first burst mode is a mode in which a first time period, during which the first and second transistors are continuously switched in the first cycle, and a second time period, during which the switching of the first and second transistors is stopped, are repeated in a predetermined cycle, and

the drive signal output circuit reduces the first time period in the predetermined cycle, in response to the output voltage rising above the first level.

2. The switching control circuit according to claim 1 , wherein the drive signal output circuit sets the first time period to a predetermined time period, in response to the output voltage reaching a second level higher than the first level.

3. The switching control circuit according to claim 2 , wherein the drive signal output circuit outputs the drive signals to stop the switching of the first and second transistors, in response to the output voltage reaching a third level higher than the second level.

4. The switching control circuit according to claim 1 , wherein

the power supply circuit further includes a first capacitor coupled in series with the primary coil, and drives a load;

the switching control circuit further includes a load detection circuit configured to detect a condition of the load of the power supply circuit, based on a resonant current of a resonant circuit that is formed by the primary coil and the first capacitor; and

the drive signal output circuit outputs the drive signals according to a second burst mode different from the first burst mode, in response to power consumed by the load becoming smaller than a first value.

5. The switching control circuit according to claim 4 , wherein the drive signal output circuit outputs the drive signals according to the second burst mode, in response to the power consumed by the load becoming smaller than the first value and the output voltage exceeding another level lower than the first level.

6. The switching control circuit according to claim 4 , wherein

the load has a rated power; and

the first value is equal to or less than 5% of the rated power of the load.

7. The switching control circuit according to claim 4 , wherein

the transformer includes an auxiliary coil,

the switching control circuit is an integrated circuit having a first terminal configured to receive a voltage corresponding to a voltage at the auxiliary coil, and

the drive signals outputted by the drive signal output circuit according to the second burst mode have a second cycle based on the voltage at the first terminal.

8. The switching control circuit according to claim 7 , further comprising:

a second terminal configured to receive an input voltage of the power supply circuit, wherein

the second cycle of the outputted drive signals is based on both the voltage at the first terminal and a voltage at the second terminal.

9. A power supply circuit configured to generate an output voltage at a target level, the power supply circuit comprising:

a transformer including a primary coil and a secondary coil;

first and second transistors configured to control a current flowing through the primary coil; and

a switching control circuit configured to control switching of the first and second transistors, wherein

the switching control circuit includes:

a drive signal output circuit configured to

output drive signals according to a normal mode, when the output voltage is lower than a first level, and

output the drive signals according to a first burst mode, when the output voltage is higher than the first level, and

a driver circuit configured to switch the first and second transistors, in response to the drive signals, wherein

the normal mode is a mode in which the first and second transistors are continuously switched, in a first cycle based on a feedback voltage corresponding to the output voltage, and

the first burst mode is a mode in which a first time period, during which the first and second transistors are continuously switched in the first cycle, and a second time period, during which the switching of the first and second transistors is stopped, are repeated in a predetermined cycle; and

the drive signal output circuit reduces the first time period in the predetermined cycle, in response to the output voltage rising above the first level.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2023
From: MATSUMOTO, HIROAKI; ASAI, JUN
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 064698/0077 →
Priority Claims (1)
JP 2022-153812 · Sep 27, 2022 · national
Continuity (1)
Related Publication 20240106334A1 · Mar 28, 2024
References Cited (20)
US 10069403B1 · Lim et al. · 2018 [cited by applicant]
US 10892688B2 · Chen · 2021 [cited by applicant]
US 20100169176A1 · Turakhia · 2010 [cited by examiner]
US 20130229829A1 · Zhang · 2013 [cited by examiner]
US 20150357927A1 · Zhang · 2015 [cited by examiner]
US 20170176918A1 · Shimura et al. · 2017 [cited by applicant]
US 20190393795A1 · Odate · 2019 [cited by examiner]
US 20200169176A1 · Murata et al. · 2020 [cited by applicant]
US 20200266704A1 · Chen · 2020 [cited by examiner]
US 20210111631A1 · Kobayashi · 2021 [cited by examiner]
US 20210184585A1 · Matsumoto · 2021 [cited by examiner]
US 20220149741A1 · Chen · 2022 [cited by examiner]
US 20220173650A1 · Araumi · 2022 [cited by examiner]
JP 2013026079A · 2013 [cited by applicant]
JP 2014108004A · 2014 [cited by applicant]
JP 2017112798A · 2017 [cited by applicant]
JP 6787505B2 · 2020 [cited by applicant]
JP 2021093813A · 2021 [cited by applicant]
JP 2021093814A · 2021 [cited by applicant]
WO 2019155733A1 · 2019 [cited by applicant]