Clock signal generator and operating method thereof
A method of generating clock signals includes: receiving a bandgap reference voltage from a bandgap reference circuit; generating a first current having a first curvature characteristic based on the bandgap reference voltage; generating a second current having a second curvature characteristic based on the bandgap reference voltage; generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current; receiving a temperature-variable voltage and a temperature-fixed voltage from a voltage generator; generating an offset current based on the temperature-variable voltage and the temperature-fixed voltage; generating a reference current by adding the first CTAT current to the offset current; and generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.
1. A method of generating clock signals, the method comprising:
receiving a bandgap reference voltage from a bandgap reference circuit;
generating a first current having a first curvature characteristic based on the bandgap reference voltage;
generating a second current having a second curvature characteristic based on the bandgap reference voltage;
generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current;
receiving a temperature-variable voltage and a temperature-fixed voltage from a voltage generator;
generating an offset current based on the temperature-variable voltage and the temperature-fixed voltage;
generating a reference current by adding the first CTAT current to the offset current; and
generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.
2. The method of claim 1 , wherein the first current is a second CTAT current in which a rate of change of current with respect to temperature increases as the temperature increases, and
wherein the second current is a third CTAT current in which a rate of change of current with respect to temperature decreases as the temperature increases.
3. The method of claim 2 , wherein a sum of the first current and the second current has a rate of change of current which is linear.
4. The method of claim 1 , wherein the offset current is a proportional to absolute temperature (PTAT) current.
5. The method of claim 4 , wherein the reference current is a constant current that is constant with respect to a temperature change.
6. The method of claim 4 , wherein the reference current is an increasing current that increases with a temperature change.
7. The method of claim 1 , wherein the offset current is a fourth CTAT current.
8. A method of generating clock signals, the method comprising:
receiving a bandgap reference voltage from a bandgap reference circuit;
generating a first current having a first curvature characteristic based on the bandgap reference voltage;
generating a second current having a second curvature characteristic based on the bandgap reference voltage;
generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current;
receiving a temperature-variable current and a temperature-fixed current from a current generator;
controlling a first p-type metal oxide semiconductor (PMOS) transistor to generate a first offset current based on the temperature-fixed current;
controlling a second PMOS transistor to generate a second offset current based on the temperature-variable current;
generating an offset current based on the first offset current and the second offset current;
generating a reference current by adding the first CTAT current to the offset current; and
generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage,
wherein a source terminal of the first PMOS transistor is connected to a source terminal of the second PMOS transistor.
9. An apparatus comprising:
a complementary to absolute temperature (CTAT) current generating circuit configured to receive a bandgap reference voltage from a bandgap reference circuit, generate a first current having a first curvature characteristic based on the bandgap reference voltage, generate a second current having a second curvature characteristic based on the bandgap reference voltage, and generate a first CTAT current by adding the first current to the second current;
an offset current generating circuit configured to receive a temperature-variable voltage and a temperature-fixed voltage from a voltage generator, generate an offset current based on the temperature-variable voltage and the temperature-fixed voltage, and generate a reference current by adding the first CTAT current to the offset current; and
a clock signal generating circuit configured to generate clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.
10. The apparatus of claim 9 , wherein the CTAT current generating circuit comprises a first curvature compensation circuit and a second curvature compensation circuit,
wherein the first curvature compensation circuit is configured to generate the first current based on a driving voltage of a first p-type metal oxide semiconductor (PMOS) transistor and the bandgap reference voltage, wherein the first current flows through a first resistor, and
wherein the second curvature compensation circuit is configured to generate the second current based on the bandgap reference voltage, wherein the second current flows through a second resistor to a ground node.
11. The apparatus of claim 9 , wherein the first current is a second CTAT current in which a rate of change of current with respect to temperature increases as the temperature increases, and
wherein the second current is a third CTAT current in which a rate of change of current with respect to temperature decreases as the temperature increases.
12. The apparatus of claim 11 , wherein a sum of the first current and the second current has a rate of change of current which is linear.
13. The apparatus of claim 9 , wherein the offset current generating circuit comprises:
a first n-type metal oxide semiconductor (NMOS) transistor configured to mirror the first CTAT current;
a first current mirror circuit configured to generate a third current by adding the mirrored first CTAT current to a first offset current;
a second current mirror circuit configured to generate a reference current based on a difference between the third current and a second offset current; and
a third current mirror circuit for mirroring the reference current.
14. The apparatus of claim 13 , wherein the temperature-fixed voltage is applied to a gate terminal of a second p-type metal oxide semiconductor (PMOS) transistor of the first current mirror circuit, the temperature-variable voltage is applied to a gate terminal of a third PMOS transistor of the second current mirror circuit, and
wherein the offset current is a proportional to absolute temperature (PTAT) current.
15. The apparatus of claim 14 , wherein the reference current is a constant current that is constant with respect to a temperature change.
16. The apparatus of claim 14 , wherein the reference current is an increasing current that increases with respect to a temperature change.
17. The apparatus of claim 13 , wherein the temperature-variable voltage is applied to a gate terminal of a second p-type metal oxide semiconductor (PMOS) transistor of the first current mirror circuit, the temperature-fixed voltage is applied to a gate terminal of a third PMOS transistor of the second current mirror circuit, and
wherein the offset current is a fourth CTAT current.
18. The apparatus of claim 9 , wherein the offset current is controlled by controlling a current mirror ratio based on a temperature code received from a digital temperature sensor.
19. The apparatus of claim 9 , wherein a frequency of a cycle of the clock signals is inversely proportional to the reference current.
20. The apparatus of claim 9 , further comprising:
a memory cell array comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines;
a row decoder configured to identify a selected memory block, from among the plurality of memory blocks, according to an address;
the voltage generator configured to provide a word line voltage to the plurality of word lines;
page buffers connected to the plurality of bit lines and configured to read data from the plurality of memory cells connected to a selected word line of the selected memory block; and
a control logic circuit configured to control, based on the clock signals, the row decoder, the voltage generator, and the page buffers.