Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors
Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.
1. A method for co-integrating a gate-all-around (GAA) nanosheet device with a comb-nanosheet device, the method comprising:
forming a GAA nanosheet device in a first region of a substrate, the GAA nanosheet device comprising a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack; and
forming a comb-nanosheet device in a second region of a substrate, the comb-nanosheet device comprising a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack, wherein the second fin spacing distance is less than the first fin spacing distance;
wherein forming the comb-nanosheet device comprises forming a shallow trench isolation (STI) liner and forming a dielectric pillar, wherein the STI liner and the dielectric pillar comprise portions of a monolithic structure;
wherein forming the comb-nanosheet device further comprises forming a first source or drain region having a first doping type and forming a second source or drain region having the first doping type; and
wherein the dielectric pillar is recessed such that the first source or drain region and the second source or drain region merge.
2. The method of claim 1 further comprising forming a same number of nanosheets in the GAA nanosheet device and the comb-nanosheet device.
3. The method of claim 1 , wherein the GAA nanosheet device and the comb-nanosheet device each comprise a same nanosheet stack height.
4. The method of claim 1 , wherein forming the comb-nanosheet device further comprises forming a first source or drain region having a first doping type and forming a second source or drain region having a second doping type opposite the first doping type.
5. The method of claim 4 , wherein the first source or drain region is isolated from the second source or drain region by the dielectric pillar.
6. The method of claim 1 , wherein the GAA nanosheet device and the comb-nanosheet device each comprise a gate spacer and a bottom isolation, wherein the gate spacer and the bottom isolation comprise portions of a monolithic structure.
7. The method of claim 6 , wherein the bottom isolation is positioned between a portion of a gate and the substrate in a gate region and between a source or drain region and the substrate in a source/drain region.