IP Library › Granted Patent US 12,414,406
Granted Patent B2
US 12,414,406 · App. 17/896,756 · Granted Sep 9, 2025

Semiconductor light-emitting device and photocoupler

Inventors: Hideto Sugawara (Nonoichi Ishikawa, JP); Hiroaki Ootsuka (Kanazawa Ishikawa, JP); Naoki Murakami (Kitakyushu Fukuoka, JP); Takanobu Kamakura (Yokosuka Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10H20/818H10F55/25H10F77/50H10F77/933H10H20/01H10H20/812H10H20/824H10H20/852H10H20/857
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,414,406
App. No.
17/896,756
Granted
Sep 9, 2025
Kind
B2
Abstract

A semiconductor light-emitting device includes a GaAs (gallium arsenide) substrate of a cubic crystal, a light-emitting layer and a multi-semiconductor layer. The light-emitting layer being provided on the GaAs substrate. The light-emitting layer includes InGaAs (indium gallium arsenide) represented by a compositional formula InxGa1-xAs (0<x<1). The multi-semiconductor layer being provided on a front surface of the GaAs substrate between the GaAs substrate and the light-emitting layer. The multi-semiconductor layer is tilted with respect to a (100) plane of the cubic crystal. The multi-semiconductor layer includes a first layer and a second layer. The first and second layers are alternately stacked in a direction perpendicular to the front surface of the GaAs substrate. The first layer is different in composition from the second layer.

Claims (38)

1. A semiconductor light-emitting device, comprising:

a GaAs (gallium arsenide) substrate of a cubic crystal;

a light-emitting layer provided on the GaAs substrate, the light-emitting layer including InGaAs (indium gallium arsenide) represented by a compositional formula In x Ga 1-x As (0<x<1); and

a multi-semiconductor layer provided on a front surface of the GaAs substrate between the GaAs substrate and the light-emitting layer, the multi-semiconductor layer being tilted with respect to a (100) plane of the cubic crystal,

the multi-semiconductor layer including a first layer and a second layer, the first layer and the second layer being alternately stacked in a direction perpendicular to the front surface of the GaAs substrate, the first layer being different in composition from the second layer.

2. The device according to claim 1 , wherein

the front surface of the GaAs substrate is tilted 8 degrees to 25 degrees with respect to the (100) plane of the cubic crystal.

3. The device according to claim 2 , wherein

the front surface of the GaAs substrate is tilted from the (100) plane in a direction toward a (011) plane, the (011) plane being orthogonal to the (100) plane.

4. The device according to claim 1 , wherein

the GaAs substrate further includes a back surface and a side surface, the back surface being at a side opposite to the front surface, the side surface being connected to the front surface and the back surface, and

at least one of the side surface of the GaAs substrate or a corner connecting the side surface and the back surface of the GaAs substrate includes a crystal dislocation extending in a direction toward the multi-semiconductor layer.

5. The device according to claim 4 , wherein

the crystal dislocation does not reach the light-emitting layer.

6. The device according to claim 4 , wherein

the side surface of the GaAs substrate is a (011) plane of the cubic crystal or a crystal plane equivalent to the (011) plane.

7. The device according to claim 6 , wherein

the crystal dislocation of the GaAs substrate extends along a crystal plane equivalent to a (111) plane of the cubic crystal.

8. The device according to claim 1 , wherein

the multi-semiconductor layer transmits light radiated from the light-emitting layer.

9. The device according to claim 1 , wherein

the first layer of the multi-semiconductor layer is an InAlP (indium aluminum phosphide) layer represented by a compositional formula In y Al 1-y P (0<y<1), and

the second layer is a GaAs layer or a AlGaAs (aluminum gallium arsenide) layer represented by a compositional formula Al v Ga 1-v As (0≤v<1).

10. The device according to claim 1 , wherein

the first layer of the multi-semiconductor layer is an InGaAs layer, and

the second layer is a GaAsP (gallium arsenide phosphide) layer represented by a compositional formula GaAs w P 1-w (0<w<1).

11. The device according to claim 1 , wherein

the light-emitting layer is included in an epitaxial layer,

the epitaxial layer includes an upper surface positioned at a side opposite to the GaAs substrate, and

the epitaxial layer includes a partial recess at an outer edge of the upper surface.

12. A photocoupler, comprising:

a light-emitting device;

a first resin sealing the light-emitting device; and

a second resin covering the first resin and the light-emitting device sealed by the first resin, the second resin having a hardness greater than a hardness of the first resin,

the light-emitting device including a GaAs substrate of a cubic crystal, a light-emitting layer and a multi-semiconductor layer,

the light-emitting layer being provided on the GaAs substrate, and including InGaAs represented by a compositional formula In x Ga 1-x As (0<x<1),

the multi-semiconductor layer being provided on a front surface of the GaAs substrate between the GaAs substrate and the light-emitting layer, the multi-semiconductor layer being tilted with respect to a (100) plane of the cubic crystal,

the multi-semiconductor layer including a first layer and a second layer, the first layer and the second layer being alternately stacked in a direction perpendicular to the front surface of the GaAs substrate, the first layer being different in composition from the second layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2022
From: SUGAWARA, HIDETO; OOTSUKA, HIROAKI; MURAKAMI, NAOKI; KAMAKURA, TAKANOBU
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 061466/0638 →
Priority Claims (1)
JP 2022-008908 · Jan 24, 2022 · national
Continuity (1)
Related Publication 20230238483A1 · Jul 27, 2023
References Cited (14)
US 5619519A · Hamada et al. · 1997 [cited by applicant]
US 5990497A · Kamakura et al. · 1999 [cited by applicant]
US 20090262770A1 · Itoh et al. · 2009 [cited by applicant]
US 20100047947A1 · Yashima · 2010 [cited by examiner]
US 20140124010A1 · Vaudo · 2014 [cited by examiner]
US 20210167231A1 · Cardwell · 2021 [cited by examiner]
US 20210222317A1 · D'Evelyn · 2021 [cited by examiner]
JP H108228047A · 1996 [cited by applicant]
JP H1074978A · 1998 [cited by applicant]
JP 2804736B2 · 1998 [cited by applicant]
JP 2804737B2 · 1998 [cited by applicant]
JP 2871609B2 · 1999 [cited by applicant]
JP 2008085301A · 2008 [cited by applicant]
Japanese Office Action issues in Japanese Patent Application No. 2022-008908, dated Dec. 25, 2024, in 5 pages. [cited by applicant]