Granted Patent B2

US 12,417,733 · App. 18/735,093 · Granted Sep 16, 2025

Inventors: Wenjun Dai (Shanghai, CN); Liang Xing (Shanghai, CN); Tianyi Wu (Shanghai, CN)

Assignee: Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd.

G09G3/32G02F1/136204G09G2300/0408G09G2300/0426G09G2310/0267G09G2310/0286G09G2310/0291

Abstract

Claims (72)

1. A display panel, comprising a display area;

wherein the display panel further comprises:

a light-emitting element, wherein the light-emitting element is located in the display area;

a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;

a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and

N pixel circuit rows and N light-emitting element rows, wherein at least one of the N pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the N pixel circuit rows and the N light-emitting element rows are arranged along a second direction, the first direction and the second direction intersect;

wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded;

a shift register circuit of the plurality of stages of shift register circuits is disposed between the j-th pixel circuit row of the N pixel circuit rows and the (j+1)-th pixel circuit row of the N pixel circuit rows, wherein j≥1, j<N and j is an integer;

wherein at least one of the following is satisfied:

no shift register circuit is disposed between an N-th pixel circuit row of the N pixel circuit rows and an (N−1)-th pixel circuit row of the N pixel circuit rows and no shift register circuit is disposed between a first pixel circuit row of the N pixel circuit rows and a second pixel circuit row of the N pixel circuit rows; or

no shift register circuit is disposed between an N-th light-emitting element row of the N light-emitting element rows and an (N−1)-th light-emitting element row of the N light-emitting element rows and no shift register circuit is disposed between a first light-emitting element row of the N light-emitting element rows and a second light-emitting element row of the N light-emitting element rows.

2. The display panel of claim 1 , wherein

no shift register circuit is disposed between the i-th pixel circuit row of the N pixel circuit rows and the (i+1)-th pixel circuit row of the N pixel circuit rows, wherein i≥1, i<N and i is an integer.

3. A display panel, comprising a display area;

wherein the display panel further comprises:

a light-emitting element, wherein the light-emitting element is located in the display area;

a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;

light-emitting element rows;

a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and

pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect;

wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded;

the display panel comprises a j-th pixel circuit row and a (j+1)-th pixel circuit row, and a shift register circuit of the plurality of stages of shift register circuits is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row, wherein j≥1 and j is an integer;

wherein at least one of the light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction, and the light-emitting element rows are arranged along the second direction;

the j-th pixel circuit row and the (j+1)-th pixel circuit row are located between a j-th light-emitting element row and (j+1)-th light-emitting element row.

4. The display panel of claim 3 , wherein

the j-th pixel circuit row is configured to drive the j-th light-emitting element row, and the j-th pixel circuit row is configured to drive the j-th light-emitting element row.

5. The display panel of claim 1 , wherein

at least one of the N light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction;

the j-th pixel circuit row is disposed on a side of the j-th light-emitting element row away from the (j+1)-th light-emitting element row, and the (j+1)-th pixel circuit row is disposed on a side of the (j+1)-th light-emitting element row facing the j-th light-emitting element row; or

the j-th pixel circuit row is disposed on a side of the j-th light-emitting element row facing the (j+1)-th light-emitting element row, and the (j+1)-th pixel circuit row is disposed on a side of the (j+1)-th light-emitting element row away from the j-th light-emitting element row.

6. The display panel of claim 5 , wherein

the j-th pixel circuit row is configured to drive the j-th light-emitting element row, and the (j+1)-th pixel circuit row is configured to drive the (j+1)-th light-emitting element row.

7. The display panel of claim 2 , wherein

the j-th pixel circuit row and the (j+1)-th pixel circuit row are located in an area of the display area, and the i-th pixel circuit row and the (i+1)-th pixel circuit row are located in another area of the display area.

8. The display panel of claim 2 , wherein

the (N−1)-th pixel circuit row and the N-th pixel circuit row are located at an edge area of the display area.

9. The display panel of claim 8 , wherein

at least one of the N light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction;

along the second direction, the N-th light-emitting element row is located on a side of the N-th pixel circuit row facing an edge area of the display area; and

the N-th pixel circuit row is configured to drive the N-th light-emitting element row.

10. The display panel of claim 2 , wherein

the driver circuit comprises a scan driver circuit and a light-emitting control driver circuit;

wherein, the scan driver circuit is configured to provide a scan signal for the pixel circuit, and the scan driver circuit comprises a plurality of stages of scan shift register circuits cascaded; and

the light-emitting control driver circuit is configured to provide a light-emitting control signal to the pixel circuit, and the light-emitting control driver circuit comprises a plurality of stages of light-emitting control shift register circuits cascaded.

11. The display panel of claim 10 , wherein

at least one scan shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row; and/or,

at least one light-emitting control shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row.

12. The display panel of claim 10 , wherein

at least one scan shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row;

the scan shift register circuit comprises a first latch module, a logic module and a first buffer module, and the first latch module, the logic module and the first buffer module are arranged along the first direction.

13. The display panel of claim 10 , wherein

at least one of the j-th pixel circuit row or the (j+1)-th pixel circuit row comprises a plurality of pixel circuit groups, and a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits;

along the first direction, a width of the scan shift register circuit is greater than a width of at least two pixel circuit groups.

14. The display panel of claim 10 , wherein

at least one light-emitting control shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row;

the light-emitting control shift register circuit comprises a second latch module and a second buffer module, and the second latch module and the second buffer module are arranged along the first direction.

15. The display panel of claim 10 , wherein

at least one of the j-th pixel circuit row or the (j+1)-th pixel circuit row comprises a plurality of pixel circuit groups, and a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits;

along the first direction, a width of the light-emitting control shift register circuit is greater than a width of at least one pixel circuit group.

16. The display panel of claim 10 , wherein

the scan shift register circuit and the light-emitting control shift register circuit are not disposed between the i-th pixel circuit row and the (i+1)-th pixel circuit row.

17. A display device comprising a display panel, wherein the display panel comprises a display area;

wherein the display panel further comprises:

a light-emitting element, wherein the light-emitting element is located in the display area;

a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;

a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and

N pixel circuit rows and N light-emitting element rows, wherein at least one of the N pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the N pixel circuit rows and the N light-emitting element rows are arranged along a second direction, the first direction and the second direction intersect;

wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded;

a shift register circuit of the plurality of stages of shift register circuits is disposed between the j-th pixel circuit row of the N pixel circuit rows and the (j+1)-th pixel circuit row of the N pixel circuit rows, wherein j≥1, j<N and j is an integer;

wherein at least one of the following is satisfied:

no shift register circuit is disposed between an N-th pixel circuit row of the N pixel circuit rows and an (N−1)-th pixel circuit row of the N pixel circuit rows and no shift register circuit is disposed between a first pixel circuit row of the N pixel circuit rows and a second pixel circuit row of the N pixel circuit rows; or

no shift register circuit is disposed between an N-th light-emitting element row of the N light-emitting element rows and an (N−1)-th light-emitting element row of the N light-emitting element rows and no shift register circuit is disposed between a first light-emitting element row of the N light-emitting element rows and a second light-emitting element row of the N light-emitting element rows.

Assignments (1)

Priority Claims (1)

Continuity (3)

References Cited (19)