Display device having gate driver
A display device including a gate driver capable of preventing threshold voltage shift of thin film transistors constituting the gate driver from influencing an output of the gate driver is disclosed. The display device includes a display panel including a plurality of gate lines and a plurality of data lines, and a gate driver including at least one scan driver. The gate driver sequentially outputs a scan signal to the plurality of gate lines. The at least one scan driver includes an output buffer configured to output a first clock signal as a scan signal in response to signals of a Q-node and a QB-node, and a first transistor configured to supply a low-level voltage to the QB-node in response to a start signal or a scan signal of an upstream stage.
1. A display device, comprising:
a display panel comprising a plurality of gate lines and a plurality of data lines; and
a gate driver comprising a plurality of scan drivers, the gate driver being configured to sequentially output a scan signal to the plurality of gate lines,
wherein one of the plurality of scan drivers comprises:
an output buffer configured to output a first clock signal as a scan signal in response to signals of a Q-node and a QB-node;
a first transistor configured to supply a low-level voltage to the QB-node in response to a start signal or a scan signal of an upstream scan driver of the plurality of scan drivers, wherein the one of the plurality of scan drivers immediately follows the upstream scan driver;
a second transistor configured to supply a high-level voltage to a Q 2 -node and the Q-node in response to the start signal or the scan signal of the upstream scan driver; and
a third transistor configured to supply the low-level voltage to a Q 1 -node in response to a voltage of a Q 2 -node in the upstream scan driver.
2. The display device according to claim 1 , wherein the one of the plurality of scan drivers further comprises:
a fourth transistor configured to supply a second clock signal to the QB-node in response to a voltage of the Q 1 -node;
a fifth transistor configured to supply the low-level voltage to the Q 1 -node in response to the first clock signal; and
a sixth transistor configured to supply the low-level voltage to the Q 2 -node in response to a voltage of the QB-node.
3. The display device according to claim 2 , wherein the one of the plurality of scan drivers further comprises:
a transfer transistor configured to transfer a voltage of the Q 2 -node to the Q-node in response to the high-level voltage.
4. The display device according to claim 2 , wherein the one of the plurality of scan drivers further comprises:
a first capacitor coupled between the Q-node and an output terminal of the output buffer;
a second capacitor coupled between the QB-node and a supply line for the low-level voltage; and
a third capacitor coupled between a supply line for the second clock signal and the Q 1 -node.
5. A display device, comprising:
a display panel comprising a plurality of gate lines and a plurality of data lines; and
a gate driver comprising a plurality of scan drivers, the gate driver being configured to sequentially output a scan signal to the plurality of gate lines,
wherein one of the plurality of scan drivers comprises:
an output buffer configured to output a first clock signal as a scan signal in response to signals of a Q-node and a QB-node;
a first transistor configured to supply a low-level voltage to the QB-node in response to a start signal or a scan signal of an upstream scan driver of the plurality of scan drivers, wherein the one of the plurality of scan drivers immediately follows the upstream scan driver; and
a first capacitor directly coupled between the QB-node and a supply line for the start signal or the scan signal of the upstream scan driver.
6. The display device according to claim 5 , wherein the one of the plurality of scan drivers further comprises:
a second transistor configured to supply a high-level voltage to a Q 2 -node and the Q-node in response to the start signal or the scan signal of the upstream scan driver;
a third transistor configured to supply the low-level voltage to a Q 1 -node in response to a voltage of a Q 2 -node in the upstream scan driver;
a fourth transistor configured to supply a second clock signal to the QB-node in response to a voltage of the Q 1 -node;
a fifth transistor configured to supply the low-level voltage to the Q 1 -node in response to the first clock signal; and
a sixth transistor configured to supply the low-level voltage to the Q 2 -node in response to a voltage of the QB-node.
7. The display device according to claim 6 , wherein the one of the plurality of scan drivers further comprises:
a transfer transistor configured to transfer a voltage of the Q 2 -node to the Q-node in response to the high-level voltage.
8. The display device according to claim 6 , wherein the one of the plurality of scan drivers further comprises:
a second capacitor coupled between the Q-node and an output terminal of the output buffer;
a third capacitor coupled between the QB-node and a supply line for the low-level voltage; and
a fourth capacitor coupled between a supply line for the second clock signal and the Q 1 -node.