Granted Patent B2

US 12,419,037 · App. 17/950,245 · Granted Sep 16, 2025

Inventors: Semyeong Jang (Hefei, CN); Joonsuk Moon (Hefei, CN); Deyuan Xiao (Hefei, CN); Jo-Lan Chin (Hefei, CN)

Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.

H10B12/315H10B12/05H10B12/482

Abstract

Claims (42)

1. A semiconductor structure, comprising:

a substrate, wherein the substrate includes a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, a plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches, and the first direction intersects with the second direction; and

a plurality of first conductive layers, wherein each of the plurality of first conductive layers is arranged on each of sidewalls, which are arrayed in the first direction, of a respective one of the plurality of active pillars, the first conductive layer is arranged on a top surface of the active pillars, and there is a gap between a bottom surface of the first conductive layer facing the substrate and a bottom surface of the second trench.

2. The semiconductor structure according to claim 1 , wherein

each of the plurality of second trenches comprises a first isolation layer and a void.

3. The semiconductor structure according to claim 2 , wherein

the void is arranged below a respective one of the plurality of first conductive layers.

4. The semiconductor structure according to claim 2 , wherein

the void is arranged between two respective first conductive layers of the plurality of first conductive layers.

5. The semiconductor structure according to claim 2 , wherein

each of the plurality of second trenches comprises a first sub-trench and a second sub-trench, and the first sub-trench is arranged above the second sub-trench, and communicates with the second sub-trench.

6. The semiconductor structure according to claim 5 , wherein

a cross-sectional area of the first sub-trench is greater than or equal to a cross-sectional area of the second sub-trench.

7. The semiconductor structure according to claim 5 , wherein

each of the plurality of first conductive layers is arranged on a sidewall, which is arranged in the first sub-trench, of a respective one of the plurality of active pillars.

8. The semiconductor structure according to claim 2 , wherein

a bit line structure is provided below a bottom portion of each of the plurality of first trenches, wherein the bit line structure extends in the first direction.

9. The semiconductor structure according to claim 8 , wherein

a first dielectric layer and a second conductive layer are provided on a sidewall, which is arranged in a respective one of the plurality of first trenches, of each of the plurality of active pillars.

10. The semiconductor structure according to claim 9 , wherein

in a section taken along the first direction, the second conductive layer is arranged above the first isolation layer and arranged in a respective one of the plurality of second trenches.

11. The semiconductor structure according to claim 10 , further comprising

a second isolation layer, wherein in the section taken along the first direction, the second isolation layer is arranged above the second conductive layer and arranged in a respective one of the plurality of second trenches; and in a section taken along the second direction, the second isolation layer is arranged between sidewalls, which are arranged in a respective one of the plurality of first trenches, of two adjacent active pillars of the plurality of active pillars.

12. The semiconductor structure according to claim 1 , wherein

a depth of each of the plurality of first trenches is less than a depth of each of the plurality of second trenches.

13. A method for manufacturing a semiconductor structure, comprising:

providing a substrate;

forming, in the substrate, a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, wherein a plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches, and the first direction intersect with the second direction; and

forming a first conductive layer on each of sidewalls, which are arrayed in the first direction, of each of the plurality of active pillars, the first conductive layer is arranged on a top surface of the active pillars, and there is a gap between a bottom surface of the first conductive layer facing the substrate and a bottom surface of the second trench.

14. The method for manufacturing the semiconductor structure according to claim 13 , wherein

in a section taken along the first direction, after a third isolation layer is formed at a bottom portion of each of the plurality of second trenches, the method further comprises: depositing a first initial conductive layer in each of the plurality of second trenches and on the third isolation layer, and removing a portion of the first initial conductive layer to remain the first initial conductive layer arranged on a sidewall, which is arranged in a respective one of the plurality of second trenches, of each of the plurality of active pillars, to form the first conductive layer.

15. The method for manufacturing the semiconductor structure according to claim 14 , wherein

each of the plurality of second trenches comprises a first sub-trench and a second sub-trench, and wherein the method further comprising: forming, in the substrate, a plurality of first sub-trenches extending in the second direction, and forming the second sub-trench at a bottom portion of a respective one of the plurality of first sub-trenches, wherein the second sub-trench communicates with the respective one of the plurality of first sub-trenches.

16. The method for manufacturing the semiconductor structure according to claim 15 , wherein

a cross-sectional area of the first sub-trench is greater than or equal to a cross-sectional area of the second sub-trench, and wherein the method further comprises: forming a first isolation layer and a void in each of the plurality of second trenches.

17. The method for manufacturing the semiconductor structure according to claim 16 , further comprising:

forming a second conductive layer on a sidewall, which is arranged in a respective one of the plurality of first trenches, of each of the plurality of active pillars, wherein in a section taken along the first direction, the second conductive layer is arranged above the first isolation layer and arranged in a respective one of the plurality of second trenches.

18. The method for manufacturing the semiconductor structure according to claim 17 , further comprising:

in the section taken along the first direction, forming, in each of the plurality of second trenches, a second isolation layer above the second conductive layer; and in a section taken along the second direction, forming the second isolation layer between sidewalls, which are arranged in a respective one of the plurality of first trenches, of two adjacent active pillars of the plurality of active pillars.

19. The method for manufacturing the semiconductor structure according to claim 13 , further comprising:

depositing a first initial dielectric layer in each of the plurality of first trenches; removing the first initial dielectric layer at a bottom portion of each of the plurality of first trenches to remain the first initial dielectric layer arranged on a sidewall of each of the plurality of first trenches to form a first dielectric layer;

and doping the bottom portion of each of the plurality of first trenches to form a bit line structure below the bottom portion of each of the plurality of first trenches, wherein the bit line structure extends in the first direction.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (40)