Semiconductor device with bit-line structure over cell region isolation film
A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride.
1. A semiconductor device comprising:
a substrate comprising a cell region;
a cell region isolation film in the substrate and extending along an outer edge of the cell region;
a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film;
a cell spacer on a vertical side surface of the distal end of the bit-line structure;
an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and
an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film comprises silicon nitride.
2. The semiconductor device of claim 1 , further comprising:
an inserted insulating film on the cell region isolation film, and on a side surface of the interlayer insulating film, wherein the inserted insulating film comprises a material different from a material of the interlayer insulating film.
3. The semiconductor device of claim 2 , wherein the inserted insulating film comprises silicon oxide.
4. The semiconductor device of claim 2 , wherein the substrate further comprises a peripheral area along a periphery of the cell region and the semiconductor device further comprises a peripheral gate structure on the substrate and in the peripheral area,
wherein the interlayer insulating film extends along a top face of the inserted insulating film and a top face of the peripheral gate structure,
wherein the inserted insulating film is between the peripheral gate structure and the interlayer insulating film.
5. The semiconductor device of claim 1 , wherein the bit-line structure comprises a first portion and a second portion including the distal end,
wherein a top face of the second portion is lower than a top face of the first portion relative to the substrate.
6. The semiconductor device of claim 1 , wherein the cell spacer comprises silicon nitride.
7. The semiconductor device of claim 1 , wherein the cell spacer comprises a material different from a material of the interlayer insulating film.
8. The semiconductor device of claim 1 , further comprising:
a cell insulating film between the substrate and the bit-line structure and disposed in the cell region,
wherein a distal end of the cell insulating film protrudes from the distal end of the bit-line structure.
9. The semiconductor device of claim 1 , further comprising:
a cell insulating film between the substrate and the bit-line structure and disposed in the cell region,
wherein the distal end of the bit-line structure protrudes from a distal end of the cell insulating film.
10. The semiconductor device of claim 1 , wherein the substrate further comprises a peripheral area along a periphery of the cell region and separated therefrom by the cell region isolation film, and the semiconductor device further comprises:
a peripheral gate structure on the substrate and in the peripheral area; and
a peripheral spacer on the cell region isolation film, wherein the peripheral spacer is between the cell spacer and the peripheral gate structure.
11. The semiconductor device of claim 10 , further comprising:
an inserted insulating film between the cell region isolation film and the interlayer insulating film,
wherein the inserted insulating film comprises a material different from silicon nitride, and
wherein a bottom face of the interlayer insulating film is in contact with the inserted insulating film and is convex toward the inserted insulating film.
12. A semiconductor device comprising:
a substrate comprising a cell region and a peripheral area along a periphery of the cell region;
a cell region isolation film in the substrate and extending along an outer edge of the cell region;
a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film;
a peripheral gate structure on the substrate and in the peripheral area;
an interlayer insulating film on the cell region isolation film and on the distal end of the bit-line structure; and
an inserted insulating film on the cell region isolation film, wherein the inserted insulating film is between the interlayer insulating film and the peripheral gate structure,
wherein a side surface of the interlayer insulating film in contact with the inserted insulating film is convex toward the inserted insulating film.
13. The semiconductor device of claim 12 , wherein the interlayer insulating film comprises a material different from a material of the inserted insulating film.
14. The semiconductor device of claim 12 , further comprising:
a cell spacer on a vertical side surface of the distal end of the bit-line structure; and
an etching stopper film extending along a side surface of the cell spacer, a top face of the cell region isolation film, and at least a portion of the peripheral gate structure,
wherein the inserted insulating film is between the etching stopper film and the interlayer insulating film.
15. The semiconductor device of claim 14 , wherein each of the interlayer insulating film and the cell spacer comprises silicon nitride.
16. The semiconductor device of claim 14 , wherein the cell spacer comprises an insulating material that is different from an insulating material of the interlayer insulating film.
17. A semiconductor device comprising:
a substrate comprising a cell region and a peripheral area along a periphery of the cell region;
a cell region isolation film in the substrate and extending along an outer edge of the cell region;
a gate electrode comprising at least a portion in the substrate and in the cell region, wherein the gate electrode extends in a first direction;
a bit-line structure on the substrate and in the cell region, wherein the bit-line structure extends in a second direction intersecting the first direction, wherein the bit-line structure has a distal end on the cell region isolation film;
a cell spacer on a side surface of the bit-line structure;
a peripheral gate structure in the peripheral area and on the substrate, wherein the peripheral gate structure is spaced apart from the bit-line structure in the second direction;
an etching stopper film extending along a side surface of the cell spacer, a top face of the cell region isolation film, and an outer face of the peripheral gate structure; and
an interlayer insulating film on the etching stopper film and on the side surface of the cell spacer, wherein the interlayer insulating film extends into at least a portion of a space between the cell spacer and the peripheral gate structure, wherein the interlayer insulating film comprises silicon nitride.
18. The semiconductor device of claim 17 , further comprising:
an inserted insulating film separated from the cell spacer by the interlayer insulating film, wherein the inserted insulating film is between the interlayer insulating film and the peripheral gate structure,
wherein the interlayer insulating film extends along a top face of the inserted insulating film and a top face of the peripheral gate structure.
19. The semiconductor device of claim 17 , wherein the interlayer insulating film fills the space between the cell spacer and the peripheral gate structure on the cell region isolation film.
20. The semiconductor device of claim 17 , wherein a bottom face of the etching stopper film is lower than a top face of the cell region isolation film relative to the substrate.