Memory device and operating method thereof
A memory device, including a memory cell array including a plurality of memory cell rows; a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data; a bit data decoder configured to: receive the bit data, and based on the bit data, generate a victim memory address including address information about the victim memory cell row; and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address.
1. A memory device comprising:
a memory cell array comprising a plurality of memory cell rows;
a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data in response to the victim memory cell row being affected by a row hammering operation;
a bit data decoder configured to:
receive the bit data, and
based on the bit data, generate a victim memory address comprising address information about the victim memory cell row; and
a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address.
2. The memory device of claim 1 , wherein the monitoring cell array comprises a plurality of monitoring cells corresponding to the plurality of memory cell rows,
wherein each monitoring cell of the plurality of monitoring cells shares a word line with a corresponding memory cell row of the plurality of memory cell rows, and
wherein the each monitoring cell is configured to detect whether the corresponding memory cell row is the victim memory cell row, and generate the bit data.
3. The memory device of claim 2 , wherein the each monitoring cell comprises a bit data generator configured to produce the bit data,
wherein the bit data generator is further configured to:
generate a first bit based on the corresponding memory cell row being determined as the victim memory cell row; and
generate a second bit based on the corresponding memory cell row being determined as a normal memory cell row, and
wherein the address information about the victim memory address corresponds to a monitoring cell which generates the first bit among the plurality of monitoring cells.
4. The memory device of claim 3 , wherein, based on all of the plurality of monitoring cells generating the second bit, the refresh manager is further configured to sequentially perform the refresh operation on the plurality of memory cell rows.
5. The memory device of claim 4 , wherein the refresh manager comprises a counter, and
wherein the refresh manager is further configured to generate a refresh address having a value which increases based on a counting operation of the counter.
6. The memory device of claim 2 , wherein the each monitoring cell comprises a transistor, a capacitor, a precharge bit line, and a bit data generator,
wherein a gate terminal of the transistor is connected to the word line,
wherein one of a source terminal and a drain terminal of the transistor is connected to the capacitor,
wherein another of the source terminal and the drain terminal of the transistor is connected to the precharge bit line, and
wherein the bit data generator is connected to the first source/drain terminal of the transistor.
7. The memory device of claim 6 ,
wherein the bit data generator is configured to:
compare a voltage applied to the capacitor with a threshold voltage;
generate a second bit based on the voltage applied to the capacitor being greater than the threshold voltage; and
generate a first bit based on the voltage applied to the capacitor dropping below the threshold voltage, and
wherein the address information about the victim memory address corresponds to a monitoring cell which generates the first bit among the plurality of monitoring cells.
8. The memory device of claim 7 , wherein, based on all of the plurality of monitoring cells generating the second bit, the refresh manager is further configured to sequentially perform the refresh operation on the plurality of memory cell rows.
9. The memory device of claim 1 , wherein the memory cell array is disposed adjacent to the monitoring cell array, and
wherein the memory cell array and the monitoring cell array share a plurality of word lines.
10. The memory device of claim 1 , wherein the monitoring cell array is spaced apart from the memory cell array, and
wherein a sub-word line driver is disposed between the monitoring cell array and the memory cell array.
11. The memory device of claim 1 , wherein the row hammering operation is applied on an adjacent memory cell row that is adjacent to the victim memory cell row.
12. An operating method of a memory device which includes a plurality of memory cell rows, the method comprising:
precharging capacitors of a plurality of monitoring cells which share word lines with the plurality of memory cell rows in order to apply an initial voltage to the capacitors;
comparing a voltage applied to each capacitor of the capacitors with a threshold voltage in order to generate bit data;
generating a victim memory address based on the bit data; and
performing a refresh operation on a victim memory cell row corresponding to the victim memory address,
wherein the generating of the bit data comprised:
generating a second bit based on the voltage applied to the each capacitor being greater than the threshold voltage; and
generating a first bit when the voltage applied to the each capacitor being below the threshold voltage, and
wherein the victim memory address includes address information about the victim memory cell row, and
wherein the address information corresponds to a monitoring cell generating the first bit among the plurality of monitoring cells.
13. The method of claim 12 , further comprising:
based on all of the plurality of monitoring cells generating the second bit, sequentially performing the refresh operation on the plurality of memory cell rows.
14. The method of claim 12 , wherein the initial voltage is greater than the threshold voltage.
15. The method of claim 14 , wherein the threshold voltage is 0.2 times to 0.4 times the initial voltage.
16. A memory system comprising:
a memory device comprising a plurality of memory cell rows; and
a memory controller configured to provide a at least one of a command signal and an address signal to the memory device in order to access data of the plurality of memory cell rows,
wherein the at least one of the command signal and the address signal comprises a refresh command and a row address,
wherein the memory device comprises:
control logic configured to receive the refresh command, and to generate a refresh enable signal;
a memory cell array comprising the plurality of memory cell rows;
a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data in response to the victim memory cell row being affected by a row hammering operation;
a bit data decoder configured to receive the bit data, and to generate a victim memory address comprising address information about the victim memory cell row; and
a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address,
wherein based on the refresh enable signal being received, the refresh manager is configured to perform the refresh operation, and
wherein the refresh enable signal is periodically generated.
17. The memory system of claim 16 , wherein the monitoring cell array comprises a plurality of monitoring cells corresponding to the plurality of memory cell rows,
wherein each monitoring cell of the plurality of monitoring cells shares a word line with a corresponding memory cell row of the plurality of memory cell rows, and
wherein the each monitoring cell is configured to detect whether the corresponding memory cell row is the victim memory cell row, and to produce the bit data.
18. The memory system of claim 17 , wherein the each monitoring cell comprises a bit data generator configured to produce the bit data,
wherein the bit data generator is further configured to:
generate a first bit based on the corresponding memory cell row being determined as the victim memory cell row; and
generate a second bit based on the corresponding memory cell row being determined as a normal memory cell row, and
wherein the address information about the victim memory address corresponds to a monitoring cell producing the first bit among the plurality of monitoring cells.
19. The memory system of claim 18 , wherein the memory cell array is disposed adjacent to the monitoring cell array, and
wherein the memory cell array and the monitoring cell array share a plurality of word lines.
20. The memory system of claim 17 , wherein the each monitoring cell comprises a transistor, a capacitor, a precharge bit line, and a bit data generator,
wherein a gate terminal of the transistor is connected to the word line,
wherein one of a source terminal and a drain terminal of the transistor is connected to the capacitor,
wherein another of the source terminal and the drain terminal of the transistor is connected to the precharge bit line, and
wherein the bit data generator is connected to the first source/drain terminal of the transistor.