Read gate training and tracking
In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.
1. A computing device, comprising:
a PHY configured to:
communicate, to a memory system, a memory read operation that includes a memory clock which correlates to a physical layer (PHY) clock;
receive a return data signal from the memory system, the return data signal including a returned data strobe that is out-of-phase with respect to the PHY clock; and
filter, using edge detection and delay adjustment, a high impedance state of the returned data strobe with respect to the PHY clock.
2. The computing device of claim 1 , wherein the PHY includes a phase detectors circuit implementing the edge detection.
3. The computing device of claim 1 , wherein the PHY is further configured to generate a pulse width filter signal to filter the high impedance state of the returned data strobe with respect to the PHY clock.
4. The computing device of claim 1 , wherein the PHY is further configured to generate a timing mask as a delay signal to filter the high impedance state of the returned data strobe with respect to the PHY clock.
5. The computing device of claim 4 , wherein the delay signal is configurable with extended pulses to filter the high impedance state, and the delay signal is self-closing.
6. The computing device of claim 4 , wherein the PHY is further configured to detect, utilize using the edge detection, a signal drift of the delay signal with respect to the returned data strobe.
7. The computing device of claim 6 , wherein the PHY is further configured to decrement the delay signal in response to detecting an advancing signal drift of the delay signal with respect to the returned data strobe.
8. The computing device of claim 6 , wherein the PHY is further configured to increment the delay signal in response to detecting a lagging signal drift of the delay signal with respect to the returned data strobe.
9. The computing device of claim 6 , wherein the PHY is configured to:
track the signal drift of the delay signal with respect to the returned data strobe during the return data signal being communicated to the memory system; and
generate the timing mask that filters the high impedance state of the returned data strobe with respect to the PHY clock during the return data signal being communicated from the memory system.
10. The computing device of claim 9 , wherein operational performance of memory operations between the PHY and the memory system is maintained based on read gate training and tracking being initiated during the return data signal communicated from the memory system.
11. A device physical layer (PHY), configured to:
communicate, to a dynamic random access memory (DRAM), a memory read operation that includes a memory clock which correlates to a PHY clock;
receive a returned data strobe from the DRAM, the returned data strobe being out-of-phase with respect to the PHY clock; and
adjust a delay signal to compensate for signal drift of the delay signal with respect to the returned data strobe.
12. The device PHY of claim 11 , wherein the device PHY is further configured to generate a pulse width filter signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.
13. The device PHY of claim 11 , wherein the device PHY is further configured to generate a timing mask as the delay signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.
14. The device PHY of claim 13 , wherein the device PHY is further configured to:
decrement the delay signal in response to detecting an advancing signal drift of the delay signal with respect to the returned data strobe; or
increment the delay signal in response to detecting a lagging signal drift of the delay signal with respect to the returned data strobe.
15. A method, comprising:
communicating, to a dynamic random access memory (DRAM), a memory read operation that includes a memory clock which correlates to a physical layer (PHY) clock;
receiving a return data signal from the DRAM, the return data signal including a returned data strobe that is out-of-phase with respect to the PHY clock; and
filtering a high impedance state of the returned data strobe with respect to the PHY clock.
16. The method of claim 15 , further comprising:
generating a pulse width filter signal to filter the high impedance state of the returned data strobe with respect to the PHY clock.
17. The method of claim 15 , further comprising:
generating a timing mask as a delay signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.
18. The method of claim 17 , further comprising:
utilizing edge detection to detect a signal drift of the delay signal with respect to the returned data strobe.
19. The method of claim 17 , further comprising:
detecting an advancing signal drift of the delay signal with respect to the returned data strobe; and
decrementing the delay signal.
20. The method of claim 17 , further comprising:
detecting a lagging signal drift of the delay signal with respect to the returned data strobe; and
incrementing the delay signal.