Code prefetch instruction
Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.
1. An apparatus comprising:
an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a relative address of a first instruction to be prefetched;
load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction; and
execution circuitry to execute the first instruction at a fetch stage of a pipeline instead of at an execute stage of the pipeline.
2. The apparatus of claim 1 , wherein the first instruction is in program code stored in a memory.
3. The apparatus of claim 1 , wherein the code prefetch instruction is to specify the relative address of the first instruction in a displacement field.
4. The apparatus of claim 1 , wherein the code prefetch instruction is to specify the relative address of the first instruction in an immediate field.
5. The apparatus of claim 1 , wherein the code prefetch instruction is to specify the relative address as an offset.
6. The apparatus of claim 5 , wherein the code prefetch instruction is to specify the relative address as an offset from an instruction pointer.
7. The apparatus of claim 2 , wherein a span of the program code to be prefetched is to be specified by a parameter of the code prefetch instruction.
8. The apparatus of claim 2 , wherein the span is to be a multiple of a size of a cache line.
9. The apparatus of claim 1 , wherein the code prefetch instruction is to provide a hint to the apparatus, wherein the processor may ignore the hint.
10. The apparatus of claim 1 , wherein a location to which the first instruction is to be prefetched is specified by a parameter of the code prefetch instruction.
11. The apparatus of claim 1 , further comprising performance monitoring hardware, wherein the performance monitoring hardware may be configured to provide information regarding an event related to performance of software using the code prefetching instruction.
12. The apparatus of claim 11 , wherein the event is related to fetch latency.
13. A method comprising:
decoding a code prefetch instruction, wherein the code prefetch instruction is to specify a relative address of a first instruction to be prefetched;
in response to the decoded code prefetch instruction, prefetching the first instruction; and
executing the first instruction at a fetch stage of a pipeline instead of at an execute stage of the pipeline.
14. The method of claim 13 , wherein the first instruction is in program code stored in the memory.
15. The method of claim 14 , wherein a span of the program code to be prefetched is to be specified by a parameter of the code prefetch instruction.
16. A system comprising:
a memory;
a processor including:
an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a relative address of a first instruction to be prefetched;
load circuitry to prefetch the first instruction from the memory in response to the decoded code prefetch instruction; and
execution circuitry to execute the first instruction at a fetch stage of a pipeline instead of at an execute stage of the pipeline.
17. The system of claim 16 , wherein the first instruction is in program code stored in the memory.