Granted Patent B2

US 12,423,153 · App. 16/694,124 · Granted Sep 23, 2025

Inventors: Zidong Du (Pudong New Area, CN); Shaoli Liu (Pudong New Area, CN); Zai Wang (Pudong New Area, CN); Tianshi Chen (Pudong New Area, CN); Shuai Hu (Pudong New Area, CN); Xuda Zhou (Pudong New Area, CN)

Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.

G06F9/505G01N30/8644G06F1/329G06F9/5038G06F9/5061G06F9/5066G06N3/02G06N3/04G06N5/01G06F2209/5017

Abstract

Claims (50)

1. A processor, comprising

a task segmentation circuit configured to segment a task into multiple subtasks according to a task segmentation granularity; and

a hardware resource division circuit configured to divide hardware resources of the processor respectively for the multiple subtasks,

wherein the task segmentation circuit includes a task segmentation granularity selection circuit configured to determine the task segmentation granularity, and

a granularity task segmentation circuit that includes:

a first granularity task segmentation circuit configured to take the whole task;

a second granularity task segmentation circuit configured to:

divide sample data associated with the task into one or more subset of sample data, and

identify a computation of each subset of sample data as one of the subtasks;

a third granularity task segmentation circuit configured to segment the task according to layer types of a neural network, where computation for layers of the same layer type is identified as one of the subtasks;

a fourth granularity task segmentation circuit configured to segment the task according to an interlayer structure of the neural network, wherein computation for multiple adjacent layers is identified as one of the subtasks; and

a fifth granularity task segmentation circuit configured to segment the task according to intra-layer structures of the neural network to segment computation types in each of the layers of the neural network into subtasks.

2. The processor of claim 1 , further comprising multiple processing elements,

wherein the hardware resource division circuit is configured to divide the multiple processing elements of the processor into multiple computation groups respectively for the multiple subtasks.

3. The processor of claim 2 , wherein the hardware resource division circuit is configured to dynamically adjust the multiple computation groups of the processing elements.

4. The processor of claim 1 , wherein the task segmentation granularity selection circuit is configured to select at least one of the first to fifth granularity task segmentation circuits for task segmentation on the basis of at least one of the number of samples to be processed of the neural network, a topological structure of the neural network and a computation amount of each layer.

5. The processor of claim 4 , further comprising a task scheduling circuit that includes:

a task queue circuit configured to cache unscheduled tasks;

a monitoring circuit configured to monitor the working state of each of multiple cores in the processor in real time; and

a task scheduling circuit configured to select a task to be scheduled from the unscheduled tasks, and allocate and schedule the task to be scheduled to a target core according to the working state of each of the multiple cores.

6. The processor of claim 5 , wherein the task scheduling circuit is configured to allocate and schedule the task to be scheduled to the target core in at least one of the following manners:

counting the number of tasks in a private task queue of each core and selecting the core with the fewest tasks in the private task queue as the target core;

tracking time for completion of all the tasks in the private task queue of each core and selecting the core of which the task completion time is shortest as the target core;

monitoring a distribution condition of resources required by the task to be scheduled in all the cores and selecting the core with the most resources as the target core;

allocating the task to be scheduled to the target core by adopting a heuristic algorithm.

7. A processing method, comprising:

segmenting, by a task segmentation circuit, a task into multiple subtasks according to a task segmentation granularity;

dividing, by a hardware resource division circuit, hardware resources of a processor respectively for the multiple subtasks;

determining, by a task segmentation granularity selection circuit, the task segmentation granularity;

taking, by a first granularity task segmentation circuit of a granularity task segmentation circuit, the whole task;

dividing, by a second granularity task segmentation circuit of the granularity task segmentation circuit, sample data associated with the task into one or more subset of sample data, and

identifying, by the second granularity task segmentation circuit of the granularity task segmentation circuit, a computation of each subset of sample data as one of the subtasks;

segmenting, by a third granularity task segmentation circuit of the granularity task segmentation circuit, the task according to layer types of a neural network, where computation for layers of the same layer type is identified as one of the subtasks;

segmenting, by a fourth granularity task segmentation circuit of the granularity task segmentation circuit, the task according to an interlayer structure of the neural network, wherein computation for multiple adjacent layers is identified as one of the subtasks; and

segmenting, by a fifth granularity task segmentation circuit of the granularity task segmentation circuit, the task according to intra-layer structures of the neural network to segment computation types in each of the layers of the neural network into subtasks.

8. The processing method of claim 7 , wherein dividing, by the hardware resource division circuit, the hardware resources of the processor according to the task segmentation result includes:

dividing, by the hardware resource division circuit, multiple processing elements of the processor into multiple computation groups respectively for the multiple subtasks.

9. The processing method of claim 8 , further comprising dynamically adjusting, by the hardware resource division circuit, the multiple computation groups of the processing elements.

10. The processing method of claim 9 , further comprising selecting, by the task segmentation granularity selection circuit, at least one of multiple granularity task segmentation circuits based on at least one of an amount of sample data to be processed in a neural network, a topological structure of the neural network, and a computation amount of each layer.

11. The processing method of claim 10 , further comprising allocating and scheduling the task after task segmentation, wherein allocating and scheduling the task after the task segmentation includes:

caching unscheduled tasks;

monitoring the working state of each core of the processor in real time; and

selecting a task to be scheduled from the unscheduled tasks, and allocating and scheduling the task to be scheduled to a target core according to the working state of each core.

12. The processing method of claim 11 , wherein allocating and scheduling the task to be scheduled to the target core includes counting a number of tasks in a private task queue of each core and selecting the core with the fewest tasks in the private task queue as the target core.

13. The processing method of claim 11 , wherein allocating and scheduling the task to be scheduled to the target core includes

tracking time for completion of all the tasks in the private task queue of each core and selecting the core of which the task completion time is shortest as the target core.

14. The processing method of claim 11 , wherein allocating and scheduling the task to be scheduled to the target core includes

monitoring a distribution condition of resources required by the task to be scheduled in all the cores and selecting the core with the most resources as the target core.

15. The processing method of claim 11 , wherein allocating and scheduling the task to be scheduled to the target core includes

allocating the task to be scheduled to the target core by adopting a heuristic algorithm.

Assignments (1)

Priority Claims (1)

Continuity (3)

References Cited (73)