IP Library › Granted Patent US 12,424,259
Granted Patent B2
US 12,424,259 · App. 18/202,149 · Granted Sep 23, 2025

Techniques for flexible self-refresh of memory arrays

Inventors: Anthony D. Veches (Boise, ID); Scott E. Smith (Plano, TX)
Assignee: Micron Technology, Inc.
G11C11/406
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Quick Facts
Patent No.
US 12,424,259
App. No.
18/202,149
Granted
Sep 23, 2025
Kind
B2
Abstract

Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

Claims (68)

1. A method, comprising:

receiving a refresh command for a memory bank associated with a memory device, each of one or more memory row addresses of a set of memory row addresses corresponding to each of one or more memory cells of a set of memory cells associated with the memory bank;

determining a value indicating a respective memory row address associated with the memory bank, the respective memory row address corresponding to a range of memory row addresses of the set of memory row addresses associated with the memory bank;

comparing a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value; and

processing the refresh command based at least in part on the comparing.

2. The method of claim 1 , wherein determining the value comprises:

retrieving, from a register, the value indicating the respective memory row address associated with the memory bank.

3. The method of claim 1 , further comprising:

determining a refresh region associated with the memory bank based at least in part on the refresh memory row address associated with the refresh command being equal to or less than the respective memory row address associated with the determined value; and

selecting a first subset of memory row addresses of the set of memory row addresses based at least in part on the determined refresh region, the selected first subset of memory row addresses corresponding to a first subset of memory cells of the set of memory cells associated with the memory bank,

wherein processing the refresh command comprises executing the refresh command for the selected first subset of memory row addresses.

4. The method of claim 3 , wherein executing the refresh command comprises:

refreshing the selected first subset of memory row addresses based at least in part on the refresh command; and

refraining from refreshing a second subset of memory row addresses based at least in part on the refresh command, the second subset of memory row addresses corresponding to a second subset of memory cells of the set of memory cells associated with the memory bank.

5. The method of claim 4 , wherein refraining from refreshing the second subset of memory row addresses comprises:

skipping the second subset of memory row addresses during a refresh operation associated with the refresh command.

6. The method of claim 3 , wherein the selected first subset of memory row addresses comprises two or more consecutive memory row addresses.

7. The method of claim 3 , wherein the selected first subset of memory row addresses comprises two or more nonconsecutive memory row addresses.

8. The method of claim 1 , further comprising:

determining a refresh region associated with the memory bank based at least in part on the refresh memory row address associated with the refresh command being equal to or less than the respective memory row address indicated by the determined value; and

selecting a first subset of memory row addresses of the set of memory row addresses based at least in part on the determined refresh region, the selected first subset of memory row addresses corresponding to a first subset of memory cells of the set of memory cells associated with the memory bank,

wherein processing the refresh command comprises executing the refresh command for the selected first subset of memory row addresses.

9. The method of claim 1 , further comprising:

determining a refresh region associated with the memory bank based at least in part on the refresh memory row address associated with the refresh command being unequal to or greater than the respective memory row address indicated by the determined value,

wherein processing the refresh command comprises rejecting the refresh command.

10. The method of claim 9 , wherein rejecting the refresh command comprises:

refraining from refreshing each of the one or more memory row addresses of the set of memory row addresses based at least in part on the rejected refresh command.

11. A method, comprising:

tracking a respective memory access for each of one or more memory row addresses of a set of memory row addresses;

setting the respective memory row address in a register based at least in part on the tracking of the respective memory access for each of the one or more memory row addresses of the set of memory row addresses;

receiving a refresh command for a memory bank associated with a memory device, each of the one or more memory row addresses of the set of memory row addresses corresponding to respective one or more memory cells of a set of memory cells associated with the memory bank;

determining a value indicating a respective memory row address associated with the memory bank based at least in part on the setting;

comparing a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value; and

processing the refresh command based at least in part on the comparing.

12. The method of claim 11 , further comprising:

storing the set respective memory row address at the memory bank.

13. The method of claim 11 , further comprising:

monitoring a respective activate command for each of the one or more memory row addresses of the set of memory row addresses,

wherein comparing the refresh memory row address associated with the refresh command is further based at least in part on monitoring the respective activate command for each of the one or more memory row addresses of the set of memory row addresses.

14. The method of claim 13 , further comprising:

determining whether the respective memory access for each of the one or more memory row addresses of the set of memory row addresses satisfies a range of memory row addresses of the set of memory row addresses associated with the memory bank based at least in part on the comparing,

wherein processing the refresh command is further based at least in part on determining whether the respective memory access for each of the one or more memory row addresses of the set of memory row addresses satisfies the range of memory row addresses of the set of memory row addresses associated with the memory bank.

15. A method, comprising:

receiving a refresh command for a memory bank associated with a memory device, each of one or more memory row addresses of a set of memory row addresses corresponding to respective one or more memory cells of a set of memory cells associated with the memory bank;

determining a value indicating a respective memory row address associated with the memory bank;

comparing a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value;

processing the refresh command based at least in part on the comparing;

receiving a command to update the value with a different respective memory row address associated with the memory bank; and

resetting the value based at least in part on the received command.

16. The method of claim 1 , further comprising:

receiving a command to reset the value associated with the memory bank,

wherein the reset nulls the value corresponding to the range of memory row addresses of the set of memory row addresses associated with the memory bank.

17. A method, comprising:

receiving a refresh command for a memory bank associated with a memory device, each of one or more memory row addresses of a set of memory row addresses corresponding to respective one or more memory cells of a set of memory cells associated with the memory bank;

determining a value indicating a respective memory row address associated with the memory bank, wherein the respective memory row address corresponds to a highest memory row address of the set of memory row addresses associated with the memory bank;

comparing a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value; and

processing the refresh command based at least in part on the comparing.

18. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

receive a refresh command for a memory bank associated with a memory device, each of one or more memory row addresses of a set of memory row addresses corresponding to each of one or more memory cells of a set of memory cells associated with the memory bank;

determine a value indicating a respective memory row address associated with the memory bank, wherein the respective memory row address corresponds to a range of memory row addresses of the set of memory row addresses associated with the memory bank;

compare a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value; and

process the refresh command based at least in part on the comparing.

19. An apparatus, comprising:

a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:

receive a refresh command for a memory bank associated with the memory device, each of one or more memory row addresses of a set of memory row addresses corresponding to each of one or more memory cells of a set of memory cells associated with the memory bank;

determine a value indicating a respective memory row address associated with the memory bank, wherein the respective memory row address corresponds to a range of memory row addresses of the set of memory row addresses associated with the memory bank;

compare a refresh memory row address associated with the refresh command to the respective memory row address indicated by the determined value; and

process the refresh command based at least in part on the comparing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2023
From: VECHES, ANTHONY D.; SMITH, SCOTT E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 063834/0014 →
Continuity (2)
Provisional Application 63348322 · Jun 2, 2022
Related Publication 20230395116A1 · Dec 7, 2023
References Cited (1)
US 10790005B1 · He · 2020 [cited by examiner]