Memory device and manufacturing thereof
View Patent ↗Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.
1. A memory bit cell, comprising:
a device layer comprising:
a first fin structure and a second fin structure each extending along a first direction; and
a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure each extending along a second direction and sequentially arranged in the first direction, wherein:
the second direction is substantially perpendicular to the first direction, and
the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure each overlie the first fin structure and the second fin structure;
a front side interconnect structure disposed above the device layer, wherein the front side interconnect structure comprises:
a bit line extending along the first direction;
a bit line bar extending along the first direction;
a word line landing extending along the first direction and overlying at least the first gate structure and the fourth gate structure; and
a first word line extending along the second direction and electrically connected to the word line landing; and
a back side interconnect structure comprising:
a voltage supply line; and
a ground line.
2. The memory bit cell of claim 1 , wherein the front side interconnect structure further comprises a second word line extending along the second direction.
3. The memory bit cell of claim 1 , further comprising:
a first line section and a second line section each disposed in a first conductive layer, wherein:
the first line section is in electrical communication with the bit line,
the second line section is in electrical communication with the bit line bar,
the first word line is disposed in a second conductive layer, and
the bit line and the bit line bar are disposed in a third conductive layer.
4. The memory bit cell of claim 3 , further comprising:
a front side voltage supply line disposed in the first conductive layer.
5. The memory bit cell of claim 1 , wherein:
the bit line bar and the bit line are disposed in different conductive layers,
the bit line bar is disposed in a first conductive layer,
the first word line is disposed in a second conductive layer, and
the bit line is disposed in a third conductive layer.
6. The memory bit cell of claim 1 , wherein the first fin structure is a continuous fin structure and intersects with the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure.
7. The memory bit cell of claim 6 , wherein the second fin structure is sectional and intersects with the second gate structure and the third gate structure.
8. The memory bit cell of claim 6 , further comprising:
a first dummy gate aligning with the first gate structure; and
a second dummy gate aligning with the fourth gate structure, wherein:
the second fin structure is a continuous fin structure, and
the second fin structure intersects with the first dummy gate, the second gate structure, the third gate structure, and the second dummy gate.
9. The memory bit cell of claim 8 , further comprising:
a front side voltage supply line extending along the first direction and disposed in a conductive layer, wherein the first dummy gate and the second dummy gate are electrically connected to the front side voltage supply line.
10. A SRAM (static random-access memory) bit cell, comprising:
a first doped region having a first pull-up transistor and a second pull-up transistor formed thereon, wherein the first pull-up transistor and the second pull-up transistor share a first fin structure having a first width;
a second doped region having a first pass transistor, a second pass transistor, a first pull down transistor, and a second pull down transistor, wherein:
the first pass transistor, the first pull down transistor, the second pull down transistor, and the second pass transistor are linearly arranged in the second doped region, and
the first pass transistor, the first pull down transistor, the second pull down transistor, and the second pass transistor share a second fin structure having a second width greater than the first width;
a first front side conductive layer having a bit line bar conductor formed therein;
a second front side conductive layer having a word line conductor formed therein;
a first back side conductive layer having a supply voltage line formed therein; and
a second back side conductive layer having a ground line formed therein.
11. The SRAM bit cell of claim 10 , wherein the first front side conductive layer is disposed over the first doped region and the second doped region and under the second front side conductive layer.
12. The SRAM bit cell of claim 10 , wherein the second front side conductive layer is disposed over the first doped region and the second doped region and under the first front side conductive layer.
13. The SRAM bit cell of claim 10 , further comprising:
a third front side conductive layer having a bit line conductor formed therein, wherein the second front side conductive layer is disposed between the first front side conductive layer and the second front side conductive layer.
14. The SRAM bit cell of claim 10 , wherein:
the first front side conductive layer comprises a first conductive line and a second conductive line formed therein,
the first conductive line is connected to a gate electrode of the first pull-up transistor, and
the second conductive line is connected to a gate electrode to the second pull-up transistor.
15. An integrated circuit chip, comprising:
an array of memory bit cells arranged in columns and rows, wherein each memory bit cell comprises:
a first fin structure and a second fin structure extending along a first direction;
a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure parallelly arranged along a second direction, wherein the second direction is substantially perpendicular to the first direction;
a bit line conductor extending along the first direction;
a bit line bar conductor extending along the first direction;
a first word line extending along the second direction;
a second word line extending along the second direction, wherein:
the first word line is electrically connected to the memory bit cell, and
the second word line is connected to an adjacent memory bit cell of the array of memory bit cells in a same row;
a supply voltage line extending along the first direction and underlying the first fin structure; and
a ground line.
16. The integrated circuit chip of claim 15 , wherein the bit line conductor, the bit line bar conductor, and the first word line are disposed above the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and the supply voltage line and the ground line are disposed below the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure.
17. The integrated circuit chip of claim 16 , wherein:
the bit line bar conductor is formed in a first front side conductive layer, and
the first word line and the second word line are formed in a second front side conductive layer.
18. The integrated circuit chip of claim 17 , wherein the bit line conductor is formed in a third front side conductive layer.
19. The memory bit cell of claim 1 , wherein the word line landing is electrically connected to the first gate structure through a first conductive via and is electrically connected to the fourth gate structure through a second conductive via.
20. The memory bit cell of claim 1 , wherein the voltage supply line extends along the first direction and underlies the first fin structure.