Circuit for testing memories
A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.
1. A test circuit for testing a memory, wherein a first input end of the memory is coupled to a first register, the test circuit transmits data to the memory through a multiplexer and the first register, a second input end of the multiplexer is coupled to the test circuit, a first output end of the multiplexer is coupled to the first register, a second output end of the memory is coupled to the test circuit through a second register, and the test circuit performs following operations sequentially:
(A) writing a first data into a first address of the memory, wherein any two adjacent bits of the first address are at different levels, and any two adjacent bits of the first data are at different levels;
(B) writing a second data into a second address of the memory, wherein any two adjacent bits of the second address are at different levels, and any two adjacent bits of the second data are at different levels;
(C) reading a first output data from the first address;
(D) reading a second output data from the second address; and
(E) determining whether the first output data and the second output data are correct by comparing the first data with the first output data and comparing the second data with the second output data.
2. The test circuit of claim 1 , wherein the most significant bit of the first address is a logic 1, and the most significant bit of the first data is the logic 1.
3. The test circuit of claim 2 , wherein the most significant bit of the second address is a logic 0, and the most significant bit of the second data is the logic 0.
4. The test circuit of claim 1 , wherein the most significant bit of the first address is a logic 0, and the most significant bit of the first data is the logic 0.
5. The test circuit of claim 4 , wherein the most significant bit of the second address is a logic 1, and the most significant bit of the second data is the logic 1.
6. The test circuit of claim 1 , wherein a third input end of the multiplexer is coupled to a logic circuit to receive a function signal outputted by the logic circuit, and the multiplexer outputs signals outputted by the test circuit instead of the function signal during testing.
7. A test circuit for testing a memory, wherein a first input end of the memory is coupled to a first register, the test circuit transmits data to the memory through a multiplexer and the first register, a second input end of the multiplexer is coupled to the test circuit, a first output end of the multiplexer is coupled to the first register, a second output end of the memory is coupled to the test circuit through a second register, and the test circuit performs following operations sequentially:
(A) writing a first data into a first address of the memory, wherein all bits of the first address are at a first level, and all bits of the first data are at the first level;
(B) writing a second data into a second address of the memory, wherein all bits of the second address are at a second level, all bits of the second data are at the second level, and the second level is different from the first level;
(C) reading a first output data from the first address;
(D) reading a second output data from the second address; and
(E) determining whether the first output data and the second output data are correct by comparing the first data with the first output data and comparing the second data with the second output data.
8. The test circuit of claim 7 , wherein to test a slow-to-fall transition delay fault of a write enable signal of the memory, operation (B) further comprises controlling the write enable signal to a high level, and operation (C) further comprises controlling the write enable signal to a low level.
9. The test circuit of claim 7 , wherein the first level is a high level, and the second level is a low level.
10. The test circuit of claim 7 , wherein the first level is a low level, and the second level is a high level.
11. The test circuit of claim 7 , the test circuit further performing following operations sequentially after operation (E):
(F) writing the second data into the second address of the memory;
(G) writing the first data into the first address of the memory;
(H) reading a third output data from the second address;
(I) read a fourth output data from the first address; and
(J) determining whether the third output data and the fourth output data are correct by comparing the second data with the third output data and comparing the first data with the fourth output data.
12. The test circuit of claim 11 , wherein to test a slow-to-rise transition delay fault of a write enable signal of the memory, operation (D) further comprises controlling the write enable signal to a low level, and operation (F) further comprises controlling the write enable signal to a high level.
13. The test circuit of claim 7 , wherein a third input end of the multiplexer is coupled to a logic circuit to receive a function signal outputted by the logic circuit, and the multiplexer outputs signals outputted by the test circuit instead of the function signal during testing.
14. A test circuit for testing a memory, wherein a first input end of the memory is coupled to a first register, the test circuit transmits data to the memory through a multiplexer and the first register, a second input end of the multiplexer is coupled to the test circuit, a first output end of the multiplexer is coupled to the first register, a second output end of the memory is coupled to the test circuit through a second register, and the test circuit performs following operations sequentially:
(A) writing a first data into a target address of the memory, wherein all bits of the target address are at a same level, and all bits of the first data are at a same level;
(B) writing a second data into the target address of the memory, wherein all bits of the second data are at a same level, and the second data is different from the first data;
(C) reading an output data from the target address; and
(D) determining whether the output data is correct by comparing the output data with the second data.
15. The test circuit of claim 14 , wherein the all bits of the target address are at a low level, the all bits of the first data are at a high level, and the all bits of the second data are at the low level.
16. The test circuit of claim 14 , wherein the all bits of the target address are at a low level, the all bits of the first data are at the low level, and the all bits of the second data are at a high level.
17. The test circuit of claim 14 , wherein the output data is a first output data, and the test circuit further performs following operations sequentially after operation (D):
(E) writing the second data into the target address of the memory;
(F) writing the first data into the target address of the memory;
(G) reading a second output data from the target address; and
(H) determining whether the second output data is correct by comparing the second output data with the first data.
18. The test circuit of claim 14 , wherein a third input end of the multiplexer is coupled to a logic circuit to receive a function signal outputted by the logic circuit, and the multiplexer outputs signals outputted by the test circuit instead of the function signal during testing.