Leadframe strip with complimentary unit design
A leadframe strip includes a two-dimensional mechanically interconnected array of leadframe units including a plurality of leadframe unit pairs, the leadframe strip having an overall length and an overall width. The plurality of leadframe unit pairs each include a first leadframe design including a first plurality of tie bars and a plurality of first leads, and a second leadframe design that is different from the first leadframe design including a second plurality of tie bars, and a plurality of second leads. The first plurality of tie bars and the second plurality of tie bars are configured together to provide a plurality of continuous metal support networks that span an entirety of the overall length or the overall width.
1. A method of forming molded semiconductor packages, comprising:
providing a leadframe strip, comprising:
a two-dimensional mechanically interconnected array of leadframe units comprising a plurality of leadframe unit pairs, the leadframe strip having an overall length and an overall width, the plurality of leadframe unit pairs each including a first leadframe design including a first plurality of tie bars and a plurality of first leads, and a second leadframe design including a second plurality of tie bars and a plurality of second leads;
wherein the first plurality of tie bars are provided in a mirrored orientation relative to the second plurality of tie bars in the length or width direction, such that the first and second tie bars are configured together to provide a plurality of continuous metal support networks that span an entirety of the overall length and the overall width;
mounting an integrated circuit (IC) comprising a substrate having a semiconductor surface including circuitry electrically coupled to bond pads on each of the plurality of leadframe units, molding for encapsulating the ICs to form a plurality of the molded semiconductor packages, and singulating the leadframe strip to provide a plurality of singulated molded semiconductor packages.
2. The method of claim 1 ,
wherein the first leadframe design includes at least a first die pad, and the second leadframe design includes at least a second die pad, and
wherein the first plurality of tie bars, the second plurality of tie bars, the at least a first die pad, and the at least a second die pad are configured together to provide the plurality of continuous metal support networks.
3. The method of claim 2 , wherein the at least the first die pad and the at least the second die pad are both split die pads.
4. The method of claim 1 , wherein the plurality of continuous metal support networks are each square wave shaped.
5. The method of claim 1 , wherein the first leadframe design and the second leadframe design are mirror images of one another except for a location of a reference pin.
6. The method of claim 1 , wherein some of the first plurality of tie bars and some of the second plurality of tie bars are electrically floating.
7. The method of claim 1 , wherein the first leadframe design and the second leadframe design are exclusive of any die pad.
8. The method of claim 1 , wherein the plurality of continuous metal support networks collectively span an entirety of the overall length and the overall width.
9. The method of claim 1 , wherein the length is >250 mm and the width is >75 mm.
10. The method of claim 1 , wherein the first leadframe design and the second leadframe design have identical exposed portions of the first leads and the second leads and also identical surface mount footprints.
11. A method of forming molded semiconductor packages, comprising:
providing a leadframe strip, comprising:
a two-dimensional mechanically interconnected array of leadframe units comprising a plurality of leadframe unit pairs each including a first leadframe design including a first plurality of tie bars and a plurality of first leads, and a second leadframe design including a second plurality of tie bars and a plurality of second leads;
wherein the first plurality of tie bars are provided in a mirrored orientation relative to the second plurality of tie bars in the length or width direction, such that the first and second tie bars are configured together to provide a plurality of continuous metal support networks that span an entirety of an overall length and an overall width of the leadframe strip; and
mounting an integrated circuit (IC) comprising a substrate having a semiconductor surface including circuitry electrically coupled to bond pads on each of the plurality of leadframe units.
12. The method of claim 11 , further including covering the ICs with molding material to form a plurality of the molded semiconductor packages.
13. The method of claim 12 , further including singulating the leadframe strip to provide a plurality of singulated molded semiconductor packages.
14. The method of claim 11 , further including singulating the leadframe strip to provide a plurality of singulated semiconductor packages.
15. The method of claim 11 ,
wherein the first leadframe design includes at least a first die pad, and the second leadframe design includes at least a second die pad, and
wherein the first plurality of tie bars, the second plurality of tie bars, the at least a first die pad, and the at least a second die pad are configured together to provide the plurality of continuous metal support networks.
16. The method of claim 15 , wherein the at least the first die pad and the at least the second die pad are both split die pads.
17. The method of claim 11 , wherein the plurality of continuous metal support networks are each square wave shaped.
18. The method of claim 11 , wherein the first leadframe design and the second leadframe design are mirror images of one another except for a location of a reference pin.
19. The method of claim 11 , wherein some of the first plurality of tie bars and some of the second plurality of tie bars are electrically floating.
20. The method of claim 11 , wherein the overall length is >250 mm and the overall width is >75 mm.
21. The method of claim 11 , wherein the first leadframe design and the second leadframe design have identical exposed portions of the first leads and the second leads and also identical surface mount footprints.
22. A method of forming a molded semiconductor package, comprising:
providing a two-dimensional mechanically interconnected leadframe unit comprising a leadframe unit pair, the leadframe unit pair including a first leadframe design including a first plurality of tie bars and a plurality of first leads, and a second leadframe design including a second plurality of tie bars and a plurality of second leads;
wherein the first plurality of tie bars are provided in a mirrored orientation relative to the second plurality of tie bars in the length or width direction, such that the first and second tie bars are configured together to provide a plurality of continuous metal support networks that span an entirety of an overall length and an overall width of the leadframe strip;
mounting an integrated circuit (IC) comprising a substrate having a semiconductor surface including circuitry electrically coupled to bond pads on each of the leadframe units; and
molding for encapsulating the ICs to form a molded semiconductor packages.