Multi-chip synchronization in sensor applications
A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.
1. A system comprising a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising:
a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device;
a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet; and
a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets;
wherein:
each of the plurality of devices other than the first device use timing parameters of the synchronization packet to align its internal clock reference;
at least one device of the plurality of devices comprises a phase-locked loop used to lock its internal clock reference to timing parameters of the synchronization packet; and
the first device increases frequency of its transmission of synchronization packets when data is not required from the second device and the third device in order to enable the phase-locked loops to lock more quickly.
2. The system of Claim 1 , wherein the third device transmits the one or more second data packets after completion of transmission of the one or more first data packets.
3. The system of claim 1 , wherein the synchronization packet comprises information defining an order of transmission of data packets from the plurality of devices in response to the synchronization packet.
4. The system of claim 1 , wherein one of the one or more first data packets comprises information identifying a next device of the plurality of devices to transmit data in response to the synchronization packet.
5. The system of claim 1 , wherein the synchronization packet comprises information defining data sought from the plurality of devices.
6. The system of claim 1 , wherein timing of the synchronization packet is offset relative to the timing of the one or more first data packets and the one or more second data packets.
7. The system of Claim 1 , wherein each of the one or more first data packets and the one or more second data packets comprise respective sensor information from a respective analog-to-digital converter.
8. A method of for a system comprising a plurality of devices coupled to one another via a shared digital wired communication link, the method comprising:
periodically transmitting, by a first device of the plurality of devices, a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device;
receiving, by a second device of the plurality of devices, the synchronization packet;
transmitting, by the second device, one or more first data packets onto the shared digital wired communication link in response to the synchronization packet;
receiving, by a third device of the plurality of devices, the synchronization packet; and
transmitting, by the third device, one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets;
each of the plurality of devices other than the first device using timing parameters of the synchronization packet to align its internal clock reference;
at least one device of the plurality of devices using a phase-locked loop to lock its internal clock reference to timing parameters of the synchronization packet; and
the first device increasing frequency of its transmission of synchronization packets when data is not required from the second device and the third device in order to enable the phase-locked loops to lock more quickly.
9. The method of claim 8 , further comprising the third device transmitting the one or more second data packets after completion of transmission of the one or more first data packets.
10. The method of claim 8 , wherein the synchronization packet comprises information defining an order of transmission of data packets from the plurality of devices in response to the synchronization packet.
11. The method of claim 8 , wherein one of the one or more first data packets comprises information identifying a next device of the plurality of devices to transmit data in response to the synchronization packet.
12. The method of claim 8 , wherein the synchronization packet comprises information defining data sought from the plurality of devices.
13. The method of claim 8 , wherein timing of the synchronization packet is offset relative to the timing of the one or more first data packets and the one or more second data packets.
14. The method of claim 8 , wherein each of the one or more first data packets and the one or more second data packets comprise respective sensor information from a respective analog-to-digital converter.