Granted Patent B2

US 12,425,188 · App. 17/979,379 · Granted Sep 23, 2025

Inventor: Jong Heon Lee (Daejeon, KR)

Assignee: Electronics and Telecommunications Research Institute

H04L9/0643H04L9/0852

Abstract

Claims (17)

1. An SHA-256 quantum circuit design apparatus comprising:

a reception unit configured to receive an SHA-256 quantum circuit having a length of a critical path consisting of six adders; and

a design unit configured to design a first SHA-256 quantum circuit having the critical path length reduced to a first value by applying a path balancing technique to the received SHA-256 quantum circuit and to design a second SHA-256 quantum circuit having the critical path length reduced to a second value by applying the path balancing technique to the first SHA-256 quantum circuit to output a d+T1 value first.

2. The SHA-256 quantum circuit design apparatus of claim 1 , wherein the design unit designs the first quantum circuit that first outputs a T1 value by iteratively applying the path balancing technique a certain number of times or more.

3. The SHA-256 quantum circuit design apparatus of claim 1 , wherein the design unit designs the second SHA-256 quantum circuit in which 11 additions and one subtraction are performed per round.

4. The SHA-256 quantum circuit design apparatus of claim 3 , wherein the design unit designs the second SHA-256 quantum circuit in which eight adder circuits and one subtractor circuit are used in a round function algorithm and three adder circuits are used in a message scheduling algorithm.

5. The SHA-256 quantum circuit design apparatus of claim 1 , wherein the design unit designs the second SHA-256 quantum circuit iteratively performed a total of 65 times by applying the path balancing technique.

6. The SHA-256 quantum circuit design apparatus of claim 1 , wherein the design unit designs the second SHA-256 quantum circuit in which the critical path length per round is 3.

7. An SHA-256 quantum circuit design method comprising:

receiving an SHA-256 quantum circuit having a length of a critical path consisting of six adders; and

designing a first SHA-256 quantum circuit having the critical path length reduced to a first value by applying a path balancing technique to the received SHA-256 quantum circuit; and

designing a second SHA-256 quantum circuit having the critical path length reduced to a second value by applying the path balancing technique to the first SHA-256 quantum circuit to output a d+T1 value first.

8. The SHA-256 quantum circuit design method of claim 7 , wherein the designing the first qSHA-256 quantum circuit comprises designing the first SHA-256 quantum circuit that first outputs a T1 value by iteratively applying the path balancing technique a certain number of times or more.

9. The SHA-256 quantum circuit design method of claim 7 , wherein the designing the second SHA-256 quantum circuit comprises designing the second SHA-256 quantum circuit in which 11 additions and one subtraction are performed per round.

10. The SHA-256 quantum circuit design method of claim 9 , wherein the designing the second SHA-256 quantum circuit comprises designing the second SHA-256 quantum circuit in which eight adder circuits and one subtractor circuit are used in a round function algorithm and three adder circuits are used in a message scheduling algorithm.

11. The SHA-256 quantum circuit design method of claim 7 , wherein the designing the second SHA-256 quantum circuit comprises designing the second SHA-256 quantum circuit iteratively performed a total of 65 times by applying the path balancing technique.

12. The SHA-256 quantum circuit design method of claim 7 , wherein the designing the second SHA-256 quantum circuit comprises designing the second SHA-256 quantum circuit in which the critical path length per round is 3.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (9)