Memory arrays comprising strings of memory cells with conductive islands
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.
1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier, the channel material of the channel-material-string constructions directly electrically coupling to conductor material of the conductor tier, the conductor tier having a top surface comprising the conductor material;
the conductor tier comprising islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands, the islands being directly against bottoms of the channel-material-string constructions the islands being spaced downwardly from the top surface of the conductor material of the conductor tier; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks.
2. The memory array of claim 1 wherein the conductor material comprises conductively-phosphorus-doped semiconductive material; the islands being formed by one of ion implantation, gas phase diffusion, and plasma enhanced doping of the conductively-phosphorus-doped semiconductive material with B.
3. The memory array of claim 1 wherein the composition of the islands comprises doped material, with dopant of the doped material being at least one of B, C, N, O, Ga, and metal material.
4. The memory array of claim 1 wherein the composition of the islands comprises doped material, with total dopant concentration of the doped material being 0.05 to 30.0 atomic percent.
5. The memory array of claim 1 wherein the composition of the islands comprises doped material, with dopant of the doped material comprising C.
6. The memory array of claim 1 wherein the composition of the islands comprises doped material, with dopant of the doped material comprising O.
7. The memory array of claim 1 wherein all of individual of the bottoms of the channel-material-string constructions are directly against the island therebelow.
8. The memory array of claim 7 wherein the bottoms of the channel-material-string constructions are directly against tops of the islands.
9. The memory array of claim 1 wherein the composition of the islands comprises doped semiconductive material.
10. The memory array of claim 9 wherein dopant of the doped semiconductive material is at least one of B, C, N, O, Ga, and metal material.
11. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier, the channel material of the channel-material-string constructions directly electrically coupling to conductor material of the conductor tier;
the conductor tier comprising islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands, the islands being directly against bottoms of the channel-material-string constructions;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks; and
the conductor material comprising conductively-doped semiconductive material directly above and directly against metal material, the islands having their bottoms directly against the metal material.
12. The memory array of claim 11 wherein the conductor tier has a top surface comprising the conductor material, the islands being spaced downwardly from the top surface of the conductor material of the conductor tier.
13. The memory array of claim 11 wherein the island bottoms are directly against a top of the metal material.
14. The memory array of claim 13 wherein the conductor tier has a top surface comprising the conductor material, the islands being spaced downwardly from the top surface of the conductor material of the conductor tier.