Resistive memory elements accessed by bipolar junction transistors
Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.
1. A structure comprising:
a semiconductor substrate;
a first well in the semiconductor substrate;
a plurality of deep trench isolation regions penetrating fully through the first well, the plurality of deep trench isolation regions partially surrounding a first section of the first well;
a first bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base, the first raised semiconductor layer spaced in a lateral direction from the second raised semiconductor layer; and
a first resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, the first electrode coupled to the first terminal of the first bipolar junction transistor,
wherein the base of the first bipolar junction transistor comprises the first section of the first well.
2. The structure of claim 1 wherein the first terminal is a collector of the first bipolar junction transistor, and the second terminal is an emitter of the first bipolar junction transistor.
3. The structure of claim 1 wherein the first raised semiconductor layer of the first terminal is coupled to the first electrode of the first resistive memory element.
4. The structure of claim 1 further comprising:
a second well in the semiconductor substrate,
wherein the first section of the first well is positioned in a vertical direction between the second well and the first terminal, and the first section of the first well is positioned in the vertical direction between the second well and the second terminal.
5. The structure of claim 4 wherein the deep trench isolation regions penetrate into the second well.
6. The structure of claim 4 wherein the first well has a first conductivity type, and the second well has a second conductivity type opposite from the first conductivity type.
7. The structure of claim 1 wherein the plurality of deep trench isolation regions partially surround a second section of the first well, and further comprising:
a second bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base, the first raised semiconductor layer spaced in the lateral direction from the second raised semiconductor layer,
wherein the base of the second bipolar junction transistor comprises the second section of the first well.
8. The structure of claim 7 further comprising:
a second resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode,
wherein the second terminal of the second bipolar junction transistor is coupled to the first electrode of the second resistive memory element.
9. The structure of claim 7 further comprising:
a shallow trench isolation region positioned between the first section of the first well and the second section of the first well, the shallow trench isolation region penetrating partially through the first well.
10. The structure of claim 9 wherein the deep trench isolation regions and the shallow trench isolation region fully surround the first section of the first well.
11. The structure of claim 10 wherein the first well includes a third section positioned beneath the shallow trench isolation region, and the third section connects the first section of the first well with the second section of the first well.
12. The structure of claim 7 further comprising:
a placement structure extending across the first section of the first well and the second section of the first well, the placement structure positioned in the lateral direction between the first raised semiconductor layer and the second raised semiconductor layer of the first bipolar junction transistor.
13. The structure of claim 12 further comprising:
a shallow trench isolation region positioned between the first section of the first well and the second section of the first well, the shallow trench isolation region penetrating partially through the first well,
wherein the placement structure is positioned to overlap with the shallow trench isolation region.
14. The structure of claim 12 wherein the placement structure comprises a gate and a gate dielectric layer between the gate and the semiconductor substrate.
15. The structure of claim 1 further comprising:
a back-end-of-line stack on the semiconductor substrate, the back-end-of-line stack comprising one or more interlayer dielectric layers,
wherein the first resistive memory element is positioned in the back-end-of-line stack.
16. The structure of claim 15 wherein the back-end-of-line stack comprises a vertical interconnection in the one or more interlayer dielectric layers, and the vertical interconnection couples the first terminal of the first bipolar junction transistor to the first electrode of the first resistive memory element.
17. The structure of claim 1 further comprising:
a dielectric layer positioned between the first bipolar junction transistor and the semiconductor substrate.
18. A structure comprising: a semiconductor substrate; a plurality of shallow trench isolation regions in the semiconductor substrate; a plurality of deep trench isolation regions in the semiconductor substrate, the deep trench isolation regions penetrating to a greater depth in the semiconductor substrate than the shallow trench isolation regions; a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base, the first raised semiconductor layer spaced in a lateral direction from the second raised semiconductor layer; and a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, the first electrode coupled to the first terminal of the bipolar junction transistor, wherein the plurality of deep trench isolation regions and the plurality of shallow trench isolation regions fully surround the base of the bipolar junction transistor.
19. The structure of claim 18 further comprising:
a well in the semiconductor substrate,
wherein the base of the bipolar junction transistor comprises a section of the well.
20. A method comprising:
forming a well in a semiconductor substrate;
forming a plurality of deep trench isolation regions penetrating fully through the well, wherein the plurality of deep trench isolation regions partially surround a section of the well;
forming a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base, wherein the first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer; and
forming a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, wherein the first electrode is coupled to the first terminal of the bipolar junction transistor,
wherein the base of the bipolar junction transistor comprises the section of the well.