IP Library › Granted Patent US 12,426,331
Granted Patent B2
US 12,426,331 · App. 17/881,740 · Granted Sep 23, 2025

Power semiconductor device and method of producing a power semiconductor device

Inventors: Damiano Cassese (Villach, AT); Andreas Korzenietz (Putzbrunn, DE); Holger Schulze (Villach, AT); Frank Umbach (Munich, DE)
Assignee: Infineon Technologies AG
H10D64/01H10D62/107H10D64/111
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,426,331
App. No.
17/881,740
Granted
Sep 23, 2025
Kind
B2
Abstract

A method of producing a power semiconductor device includes: providing a semiconductor body; forming, at the semiconductor body, a polycrystalline semiconductor region; forming, at the polycrystalline semiconductor region, an amorphous sublayer; subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer; and forming a metal layer at the re-crystallized sublayer.

Claims (38)

1. A method of producing a power semiconductor device, the method comprising:

providing a semiconductor body;

forming, at the semiconductor body, a polycrystalline semiconductor region, wherein forming the polycrystalline semiconductor region includes a structuring step during which a lateral structuration of the polycrystalline semiconductor region is performed to form a laterally structured polycrystalline semiconductor region;

forming, at the polycrystalline semiconductor region, an amorphous sublayer, wherein forming the amorphous sublayer includes a damage implantation processing step, wherein the damage implantation processing step is carried out as an unmasked implantation to form a doped semiconductor region in the semiconductor body adjacent to the laterally structured polycrystalline semiconductor region;

subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer; and

forming a metal layer at the re-crystallized sublayer.

2. The method of claim 1 , wherein the damage implantation processing step includes implanting heavy ions.

3. The method of claim 2 , wherein the heavy ions have a mass equal to or greater than the mass of phosphorus ions.

4. The method of claim 2 , wherein the heavy ions include one or more of argon, boron, neon, arsenic, boron-difluoride, and trihydridoboron.

5. The method of claim 1 , wherein a dose applied during the damage implantation processing step is greater than 1*10 13 cm −2 and/or wherein an energy applied during the damage implantation processing step is greater than 15 keV.

6. The method of claim 1 , wherein the polycrystalline semiconductor region is formed as a laterally unstructured layer, and wherein the damage implantation processing step is carried out as an unmasked implantation.

7. The method of claim 1 , further comprising a dopant implantation step being separate from the damage implantation processing step.

8. The method of claim 7 , wherein species implanted during the damage implantation processing step are non-doping.

9. The method of claim 7 , wherein the dopant implantation step is carried out after the re-crystallization processing step.

10. The method of claim 7 , wherein the dopant implantation step is carried out prior to the damage implantation processing step.

11. The method of claim 1 , wherein forming the amorphous sublayer includes a deposition processing step or an amorphization processing step.

12. The method of claim 1 , wherein the re-crystallization processing step includes a temperature annealing processing step.

13. The method of claim 1 , wherein the polycrystalline semiconductor region is based on silicon.

14. The method of claim 1 , wherein the metal layer comprises Al, Cu, AlSi, AlSiCu, or AlCu.

15. The method of claim 1 , further comprising:

forming a first insulation layer at the semiconductor body, wherein during the forming of the polycrystalline semiconductor region, the polycrystalline semiconductor region is formed at least partly above the first insulation layer; and/or

forming a second insulation layer at the re-crystallized sublayer, wherein during the forming of the metal layer, the metal layer is formed at least partly above the second insulation layer.

16. A method of producing a power semiconductor device, the method comprising:

providing a semiconductor body;

forming, at the semiconductor body, a polycrystalline semiconductor region;

forming, at the polycrystalline semiconductor region, an amorphous sublayer, wherein forming the amorphous sublayer includes a damage implantation processing step;

subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer;

performing a dopant implantation step separate from the damage implantation processing step, wherein the dopant implantation step is carried out after the re-crystallization processing step; and

forming a metal layer at the re-crystallized sublayer.

17. A method of producing a power semiconductor device, the method comprising:

providing a semiconductor body;

forming, at the semiconductor body, a polycrystalline semiconductor region;

forming, at the polycrystalline semiconductor region, an amorphous sublayer;

subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer;

forming a metal layer at the re-crystallized sublayer; and

at least one of:

forming a first insulation layer at the semiconductor body, wherein during the forming of the polycrystalline semiconductor region, the polycrystalline semiconductor region is formed at least partly above the first insulation layer; and

forming a second insulation layer at the re-crystallized sublayer, wherein during the forming of the metal layer, the metal layer is formed at least partly above the second insulation layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2023
From: KORZENIETZ, ANDREAS; CASSESE, DAMIANO; UMBACH, FRANK; SCHULZE, HOLGER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 062499/0784 →
Priority Claims (1)
DE 102021121043.7 · Aug 12, 2021 · national
Continuity (1)
Related Publication 20230048908A1 · Feb 16, 2023
References Cited (19)
US 4753895A · Mayer et al. · 1988 [cited by applicant]
US 6005284A · Ejiri et al. · 1999 [cited by applicant]
US 6893929B1 · Xiang · 2005 [cited by examiner]
US 7972947B2 · Giles · 2011 [cited by examiner]
US 9269591B2 · Kalnitsky · 2016 [cited by examiner]
US 10192779B1 · Shank · 2019 [cited by examiner]
US 20060154429A1 · De et al. · 2006 [cited by applicant]
US 20080096370A1 · Anderson · 2008 [cited by examiner]
US 20090108301A1 · Yin et al. · 2009 [cited by applicant]
US 20130012008A1 · Ko · 2013 [cited by examiner]
US 20140284615A1 · Mauder · 2014 [cited by examiner]
US 20170194151A1 · Zhang et al. · 2017 [cited by applicant]
US 20180006145A1 · Xiong · 2018 [cited by examiner]
US 20190051677A1 · Liu · 2019 [cited by examiner]
US 20200381421A1 · Suganuma · 2020 [cited by applicant]
US 20210020777A1 · Pfirsch · 2021 [cited by examiner]
WO 8904548A2 · 1989 [cited by applicant]
Lutz, Josef, “Halbleiter-Leistungsbauelemente”, Physik, Eigenschaften, Zuverlässigkeit, Springer-Verlag Berlin Heidelberg, 2012, pp. 1-4. [cited by applicant]
Morehead, F. F., et al., “Formation of Amorphous Silicon by Ion Bombardment as a Function of Ion, Temperature, and Dose”, J. Appl. Phys., vol. 43, No. 3, Mar. 1972, pp. 1112-1118. [cited by applicant]