Granted Patent B2

US 12,430,031 · App. 18/641,779 · Granted Sep 30, 2025

Inventors: Siamak Tavallaei (Spring, TX); Ishwar Agarwal (Redmond, WA)

Assignee: Microsoft Technology Licensing, LLC

G06F3/061G06F3/0655G06F3/0673G06F13/1668

Abstract

Claims (55)

1. A computing device, comprising:

two or more compute nodes, each compute node comprising an independently coherent domain that is not coherent with other compute nodes; and

a central IO die communicatively coupled to each of the two or more compute nodes, the central IO die comprising:

a compute die port coupled to each compute node;

a memory port communicatively coupled to disaggregated memory at an external device via an IO port; and

a plurality of distributed home agents communicatively coupled to each compute die port, each distributed home agent communicatively coupled via a target address decoder (TAD) to at least one memory port, each distributed home agent configured to:

receive a request for disaggregated memory from a requesting compute node via a respective compute die port;

pass the received request to the TAD; and

at the TAD, map the received request to a target memory port.

2. The computing device of claim 1 , wherein the compute die port decodes an address within the received request and maps the decoded address to a respective distributed home agent.

3. The computing device of claim 1 , wherein the target memory port is coupled to the external device comprising the disaggregated memory.

4. The computing device of claim 1 , wherein the distributed home agent further comprises a cache currency mechanism comprising a snoop filter, the cache currency mechanism coupled to the TAD via content addressable memory.

5. The computing device of claim 4 , wherein the distributed home agent is further configured to:

receive a request for memory access;

using the snoop filter, determine whether an updated copy of the request for memory access exists in the content addressable memory; and

present the updated copy of the request for memory access.

6. The computing device of claim 4 , wherein the IO port further includes a serial bus interconnect (SBI) currency port configured to allow parallel lookups to external cache and to disaggregated memory.

7. The computing device of claim 6 , wherein the distributed home agent is coupled to one or more additional external devices via the IO port.

8. The computing device of claim 7 , wherein the central IO die is configured to:

receive a request for an IO virtual address from the external device via an SBI root port;

at the SBI root port, translate the IO virtual address into a known physical address;

decode the known physical address such that any request for a given physical address targets the same distributed home agent;

send the decoded known physical address to the respective distributed home agent; and

at the distributed home agent, translate the decoded known physical address for the external device.

9. The computing device of claim 1 , wherein the computing device is a multi-chiplet device.

10. A computing device, comprising:

two or more compute nodes, each compute node comprising an independently coherent domain that is not coherent with other compute nodes; and

a central IO die communicatively coupled to each of the two or more compute nodes, the central IO die comprising:

a compute die port coupled to each compute node;

a memory port communicatively coupled to disaggregated memory at an external device via an IO port; and

a plurality of distributed memory access request managers communicatively coupled to each compute die port, each distributed memory access request manager communicatively coupled via a memory access routing agent to at least one memory port, each distributed memory access request manager configured to:

receive a request for disaggregated memory from a requesting compute node via a respective compute die port;

pass the received request to the memory access routing agent;

at the memory access routing agent, map the received request to a target memory port.

11. The computing device of claim 10 , wherein the compute die port decodes an address within the received request and maps the decoded address to a respective distributed memory access request manager.

12. The computing device of claim 10 , wherein the target memory port is coupled to the external device comprising the disaggregated memory.

13. The computing device of claim 10 , wherein the distributed memory access request manager further comprises a cache currency mechanism comprising a snoop filter, the cache currency mechanism coupled to the memory access routing agent via content addressable memory.

14. The computing device of claim 13 , wherein the distributed memory access request manager is further configured to:

receive a request for memory access;

using the snoop filter, determine whether an updated copy of the request for memory access exists in the content addressable memory; and

present the updated copy of the request for memory access.

15. The computing device of claim 13 , wherein the IO port further includes a serial bus interconnect (SBI) currency port configured to allow parallel lookups to external cache and to disaggregated memory.

16. The computing device of claim 15 , wherein the distributed memory access request manager is coupled to one or more additional external devices via the IO port.

17. The computing device of claim 16 , wherein the central IO die is configured to:

receive a request for an IO virtual address from the external device via an SBI root port;

at the SBI root port, translate the IO virtual address into a known physical address;

decode the known physical address such that any request for a given physical address targets the same distributed memory access request manager;

send the decoded known physical address to the respective distributed memory access request manager; and

at the distributed memory access request manager, translate the decoded known physical address for the external device.

18. The computing device of claim 10 , wherein the computing device is a multi-chiplet device.

19. A method for a computing device comprising a central IO die communicatively coupled to two or more compute nodes, each compute node comprising an independently coherent domain that is not coherent with other compute nodes, the method comprising:

at a home agent communicatively coupled to one of the compute nodes via a compute die port, receiving a request for disaggregated memory at an external device from the communicatively coupled compute node, the disaggregated memory communicatively coupled to a first memory port of the central IO die via an IO port;

passing the received request to a target address decoder (TAD) communicatively coupled to at least the first memory port via the home agent; and

at the TAD, mapping the received request to the first memory port.

20. The method of claim 19 , wherein the computing device is a multi-chiplet device.

Assignments (1)

Continuity (3)

References Cited (9)