Multistage compiler architecture
A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
1. A system, comprising:
a computing device including a processor;
a compiler running on the computing device, wherein the compiler includes a plurality of compiler blocks, wherein compiler blocks of the plurality of compiler blocks are compossible, and wherein the compiler is configured to
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code associated with an application;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware,
wherein the compiler comprises a frontend compiler and a backend compiler, and wherein the backend compiler comprises the plurality of compiler blocks, and wherein the plurality of compiler blocks is configured to generate a plurality of structured metadata that includes information associated with the the one or more resources in the hardware and the one or more processing operations, and wherein a structured metadata from the plurality of structured metadata is selected and fed back into one compiler block of the plurality of compiler blocks of the backend compiler, and wherein the selected structured metadata is used by the one compiler block of the plurality of compiler blocks of the backend compiler.
2. The system of claim 1 , wherein the plurality of structured metadata provides information associated with memory location storing data, and wherein the memory location storing the data is compared to expected data for verification of the high-level function.
3. The system of claim 1 , wherein the plurality of structured metadata provides information associated with memory location storing data, and wherein the memory location storing the data is compared to expected data for debugging of the high-level function.
4. The system of claim 1 , wherein a compiler block of the plurality of compiler blocks is replaceable with a different compiler block.
5. The system of claim 1 , wherein a compiler block of the plurality of compiler blocks is replaceable with a compiler block that includes experimental algorithms for a different mapping strategy or memory allocation.
6. The system of claim 1 , wherein a compiler block of the plurality of compiler blocks is replaceable with a compiler block that includes a debug version of the compiler block being replaces.
7. The system of claim 6 , wherein the debug version compiler block is configured to store data associated with compilation and modify internal representation and metadata that results in debug binary.
8. The system of claim 1 , wherein the one or more processing operations is one of changing precision, quantization, dimension reordering, or splitting or copying data across one or more processing tiles of the hardware.
9. The system of claim 1 , wherein the one or more processing operations reduces data movement.
10. The system of claim 1 , wherein the one or more processing operations reduces storage.
11. The system of claim 1 , wherein the one or more processing operations reduces computations.
12. The system of claim 1 , wherein the one or more processing operations reduces data conversion.
13. The system of claim 1 , wherein determining resources in the hardware includes mapping of operations and data to one or more tiles of the hardware to execute the set of low-level instructions.
14. The system of claim 1 , wherein the hardware is a machine learning (ML) hardware, and wherein the application is an ML operation.
15. The system of claim 1 , wherein the hardware is a dedicated hardware block including one or more microprocessors and/or on-chip memory (OCM) units storing the data and/or the set of low-level instructions compiled from the high-level function.
16. The system of claim 1 , wherein the compiler is further configured to:
receive a high-level function in a high-level code of an application;
divide the high-level function into core parts; and
check for lexical, grammar, and syntax.
17. A system, comprising:
a compiler comprising a frontend compiler and a backend compiler;
a first output module coupled to the frontend compiler, wherein the first output module is configured to output data renderable to provide information associated with incorrect command line, guidance on correct usage, identification of unsupported operators, or ill-formed networks; and
a second output module coupled to the backend compiler, wherein the second output module is configured to output data renderable to provide information associated with incorrect command line, guidance on correct usage, identification of unsupported operators, or ill-formed networks,
wherein the compiler is configured to:
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware.
18. The system of claim 17 , wherein the backend compiler comprises:
a plurality of compiler blocks, wherein compiler blocks of the plurality of compiler blocks are compossible.
19. The system of claim 18 , wherein the plurality of compiler blocks is configured to generate a plurality of structured metadata that includes information associated with the determining resources in the hardware and one or more processing operations, and wherein a structured metadata from the plurality of structured metadata is selected and fed back into one backend compiler of the plurality of backend compilers, and wherein the selected structured metadata is used by the one backend compiler to optimize its operation.
20. The system of claim 19 , wherein the plurality of structured metadata provides information associated with memory location storing data, and wherein the memory location storing the data is compared to expected data for verification of the high-level function.
21. The system of claim 19 , wherein the plurality of structured metadata provides information associated with memory location storing data, and wherein the memory location storing the data is compared to expected data for debugging of the high-level function.
22. The system of claim 18 , wherein a compiler block of the plurality of compiler blocks is replaceable with a different compiler block.
23. The system of claim 18 , wherein a compiler block of the plurality of compiler blocks is replaceable with a compiler block that includes experimental algorithms for a different mapping strategy or memory allocation.
24. The system of claim 18 , wherein a compiler block of the plurality of compiler blocks is replaceable with a compiler block that includes a debug version of the compiler block being replaces.
25. The system of claim 24 , wherein the debug version compiler block is configured to store data associated with compilation and modify internal representation and metadata that results in debug binary.
26. The system of claim 17 , wherein the one or more processing operations is one of changing precision, quantization, dimension reordering, or splitting or copying data across one or more processing tiles of the hardware.
27. The system of claim 17 , wherein the one or more processing operations reduces data movement.
28. The system of claim 17 , wherein the one or more processing operations reduces storage.
29. The system of claim 17 , wherein the one or more processing operations reduces computations.
30. The system of claim 17 , wherein the one or more processing operations reduces data conversion.
31. The system of claim 17 , wherein determining resources in the hardware includes mapping of operations and data to one or more tiles of the hardware to execute the set of low-level instructions.
32. The system of claim 17 , wherein the hardware is a machine learning (ML) hardware, and wherein the application is an ML operation.
33. The system of claim 17 , wherein the hardware is a dedicated hardware block including one or more microprocessors and/or on-chip memory (OCM) units storing the data and/or the set of low-level instructions compiled from the high-level function.
34. The system of claim 17 , wherein the compiler is further configured to:
receive a high-level function in a high-level code of an application;
divide the high-level function into core parts; and
check for lexical, grammar, and syntax.
35. A method, comprising:
identifying one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;
determining one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware;
compiling the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware,
wherein a plurality of blocks of a compiler performing the identifying, the determining, and the compiling, are compossible, and wherein a block of the plurality of blocks of the compiler is replaceable with another compiler block that includes experimental algorithms for a different mapping strategy or memory allocation or a debug version of the compiler block being replaced.
36. A method, comprising:
identifying one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;
determining one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware;
compiling the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware; and
outputting data renderable to a user to provide information associated with incorrect command line, guidance on correct usage, identification of unsupported operators, or ill-formed networks.
37. A system, comprising:
a means for identifying one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;
a means for determining one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware;
a means for compiling the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware,
wherein the means for identifying, the means for determining, and the means for compiling are compossible, and wherein a compiler block of a plurality of blocks of the compiler is replaceable with another compiler block that includes experimental algorithms for a different mapping strategy or memory allocation or a debug version of the compiler block being replaced.
38. A system, comprising:
a first means comprising a frontend compiler and a backend compiler, wherein the means is configured to:
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware;
a second means coupled to the frontend compiler for outputting data renderable to provide information associated with incorrect command line, guidance on correct usage, identification of unsupported operators, or ill-formed networks; and
a third means coupled to the backend compiler for outputting data renderable to provide information associated with incorrect command line, guidance on correct usage, identification of unsupported operators, or ill-formed networks.
39. A system, comprising:
a computing device comprising a processor;
a compiler running on the computing device, wherein the compiler includes a plurality of compiler blocks, wherein compiler blocks of the plurality of compiler blocks are compossible, wherein a compiler block of the plurality of compiler blocks is replaceable with another compiler block that includes experimental algorithms for a different mapping strategy or memory allocation, and wherein the compiler is configured to
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code associated with an application;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
40. A system, comprising:
a computing device comprising a processor;
a compiler running on the computing device, wherein the compiler includes a plurality of compiler blocks, wherein compiler blocks of the plurality of compiler blocks are compossible, wherein a compiler block of the plurality of compiler blocks is replaceable with another compiler block that includes a debug version of the compiler block being replaced, and wherein the compiler is configured to
identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code associated with an application;
determine one or more processing operations to be performed that is associated with the high-level function in the high-level code, and wherein the determining of the one or more processing operations occurs based on architecture of the hardware; and
compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.