Multi-processor bridge with cache allocate awareness
Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.
1. A system comprising:
a processor package including a plurality of processors and a cache memory coupled to the plurality of processors; and
a shared memory controller coupled to the processor package and configured to:
receive a memory management command including a first indication of a memory operation and a second indication of a memory location in the cache memory, wherein the first indication specifies that the memory operation is a prewarming operation for the memory location in the cache memory;
format the memory management command into a formatted command;
route the formatted command to the processor package; and
receive a response from the processor package indicating that the memory operation was successful.
2. The system of claim 1 ,
wherein the processor package further includes a cache memory controller coupled to the cache memory, and
wherein the shared memory controller is configured to route the formatted command to the cache memory controller.
3. The system of claim 2 , wherein the cache memory controller is configured to send the response indicating that the memory operation was successful to the shared memory controller.
4. The system of claim 1 , wherein the plurality of processors include a first processor core configured to:
execute the memory operation; and
load data into the memory location of the cache memory.
5. The system of claim 1 ,
wherein to format the memory management command, the shared memory controller is configured to format the memory management command into a read op code, and
wherein the shared memory controller is configured to route the read op code to the processor package.
6. The system of claim 5 , wherein the response from the processor package indicates that a loading of data into the memory location was successful.
7. The system of claim 1 , wherein the processor package is configured to:
schedule a second process for execution after a currently running first process; and
issue the memory management command to the shared memory controller to prewarm the cache memory before switching from the currently running first process to the second process.
8. The system of claim 7 ,
wherein the plurality of processors includes a first processor, and
wherein the processor package is configured to:
schedule the second process for execution on the first processor; and
select the memory location in the memory management command based on the first processor,
wherein the memory location is shared by the first processor.
9. The system of claim 1 ,
wherein the processor package is a first processor package,
wherein the plurality of processors is a first plurality of processors,
wherein the system further comprises a second processor package including a second plurality of processors,
wherein the cache memory includes an L2 cache memory shared by the plurality of processors in the first processor package, and
wherein the L2 cache memory is not shared with the second plurality of processors in the second processor package.
10. The system of claim 1 ,
wherein the memory management command is a first command,
wherein the shared memory controller includes an L3 cache memory;
wherein the shared memory controller is configured to:
receive a second memory management command;
format the second memory management command as a read op; and
route the read op to the L3 cache memory.
11. The system of claim 1 , further comprising a bridge circuit coupled to the shared memory controller,
wherein the memory management command is a first command,
wherein the shared memory controller is configured to:
receive a second memory management command;
format the second memory management command into a second formatted command; and
route the second formatted command to the bridge circuit.
12. The system of claim 11 ,
wherein the plurality of processors includes a first processor including a memory interface, and
wherein the bridge circuit is configured to:
translate the second formatted command into an op code; and
transmit the op code to the memory interface of the first processor.
13. A method comprising:
receiving a first memory management command including a first indication of a memory operation and a second indication of a memory location in a cache memory in a processor package, wherein the first indication specifies that the memory operation is a prewarming operation for the memory location in the cache memory;
formatting the first memory management command into a formatted command;
routing the formatted command to the processor package; and
receiving a response from the processor package indicating that the memory operation was successful.
14. The method of claim 13 , further comprising:
receiving a second memory management command;
formatting the second memory management command as a read op; and
routing the read op to a L3 cache memory.
15. The method of claim 13 , further comprising:
receiving a second memory management command;
formatting the second memory management command into a second formatted command; and
routing the second formatted command to a bridge circuit.
16. A system comprising:
a processor package including:
a plurality of processors;
a cache memory coupled to the plurality of processors; and
a cache memory controller coupled to the cache memory, wherein the processor package is configured to:
schedule a second process for execution after a currently running first process; and
issue a first prewarming command to prewarm a location in the cache memory before switching from the currently running first process to the second process; and
a shared memory controller coupled to the processor package and configured to:
format the first prewarming command into a first formatted command;
route the first formatted command to the cache memory controller; and
receive a response from the cache memory controller indicating that a loading of data into the location was successful.
17. The system of claim 16 ,
wherein the shared memory controller includes an L3 cache memory;
wherein the shared memory controller is configured to:
receive a second prewarming command;
format the second prewarming command as a read op; and
route the read op to the L3 cache memory.
18. The system of claim 16 , further comprising a bridge circuit coupled to the shared memory controller, wherein the shared memory controller is configured to:
receive a second prewarming command;
format the second prewarming command into a second formatted command; and
route the second formatted command to the bridge circuit.
19. The system of claim 18 ,
wherein the plurality of processors includes a first processor including a memory interface, and
wherein the bridge circuit is configured to:
translate the second formatted command into an op code; and
transmit the op code to the memory interface of the first processor.