Display device
A display device including a light-emitting diode, a first transistor, a second transistor, a data line connected to the second transistor and configured to transmit a data signal, a third transistor, a first signal line connected to a gate electrode of the second transistor and configured to transmit a first signal, a second signal line connected to a gate electrode of the third transistor and configured to transmit a second signal, and a connect portion connected to a gate electrode of the first transistor and an electrode of the third transistor, in which the connect portion overlaps the first signal line and the second signal line, and an overlapping area between the connect portion and the first signal line is different from an overlapping area between the connect portion and the second signal line.
1. A display device comprising:
a light-emitting diode;
a first transistor electrically connected to the light-emitting diode to supply a driving current to the light-emitting diode, the first transistor comprising a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first electrode, and a second electrode which is electrically connected to the light-emitting diode;
a first scan line configured to transmit a first signal to a second gate electrode of a second transistor, the second gate electrode being a portion of the first scan line;
a second scan line configured to transmit a second signal to a third gate electrode of a third transistor, the third gate electrode being a portion of the second scan line; and
a conductive pattern physically connected to the first gate electrode,
wherein:
the conductive pattern overlaps the first scan line and the second scan line in the plan view; and
one of the second transistor and the third transistor is a PMOS transistor, and the other one of the second transistor and the third transistor is an NMOS transistor.
2. The display device of claim 1 , wherein an overlapping area of the conductive pattern and the first scan line is different from an overlapping area of the conductive pattern and the second scan line.
3. The display device of claim 2 , wherein the overlapping area of the conductive pattern and the first scan line is larger than the overlapping area of the conductive pattern and the second scan line.
4. The display device of claim 3 , wherein the second transistor is the PMOS transistor, and the third transistor is the NMOS transistor.
5. The display device of claim 4 , further comprising a data line,
wherein the second transistor further comprises a second channel region overlapping the second gate electrode in the plan view, a third electrode physically connected to the data line, and a fourth electrode physically connected to the first electrode.
6. The display device of claim 4 , wherein the third transistor further comprises a third channel region overlapping the third gate electrode in the plan view, a fifth electrode physically connected to the second electrode, and a sixth electrode physically connected to the conductive pattern.
7. The display device of claim 6 , wherein the sixth electrode and the conductive pattern are formed in one body.
8. The display device of claim 5 , wherein the first transistor is the PMOS transistor.
9. The display device of claim 1 , wherein a first capacitance between the conductive pattern and the first scan line is configured to be greater than a second capacitance between the conductive pattern and the second scan line.
10. The display device of claim 1 , wherein the conductive pattern comprises:
a stem part extending in one direction; and
a branch part branching from the stem part and overlapping the first scan line.
11. The display device of claim 1 , wherein:
the first signal comprises a first logic high level and a first logic low level;
the second signal comprises a second logic high level and a second logic low level; and
the first signal having the first logic low level and the second signal having the second logic high level are configured to be transmitted at the same point of time.
12. The display device of claim 1 , further comprising:
a substrate;
a first semiconductor layer disposed on the substrate, the first semiconductor layer comprising a second channel region of the second transistor overlapping the second gate electrode in the plan view;
a first insulating layer disposed on the first semiconductor layer;
a first conductive layer disposed on the first insulating layer, the first conductive layer comprising the first scan line extending in a first direction;
a second insulating layer disposed on the first conductive layer;
a second conductive layer disposed on the second insulating layer, the second conductive layer comprising the second scan line extending in the first direction;
a third insulating layer disposed on the second conductive layer;
a second semiconductor layer disposed on the third insulating layer, the second semiconductor layer comprising a third channel region of the third transistor overlapping the third gate electrode in the plan view; and
a third conductive layer disposed on the second semiconductor layer, the third conductive layer comprising the conductive pattern.
13. The display device of claim 12 , wherein:
the third transistor further comprises a third electrode and a fourth electrode;
the third electrode and the fourth electrode are disposed on the third channel region; and
one of the third electrode and the fourth electrode is a portion of the conductive pattern.
14. The display device of claim 12 , further comprising:
a fourth insulating layer disposed on the third conductive layer; and
a fourth conductive layer disposed on the fourth insulating layer,
wherein the fourth conductive layer comprises a first supply voltage line which is electrically connected to the first electrode.
15. The display device of claim 14 , wherein the first supply voltage line is overlapped with the third channel region in the plan view.
16. A display device comprising:
a light-emitting diode;
a first transistor electrically connected to the light-emitting diode to supply a driving current to the light-emitting diode, the first transistor comprising a first gate electrode, a first channel region, a first electrode, and a second electrode which is electrically connected to the light-emitting diode;
a second transistor, the second transistor comprising a second gate electrode which is a portion of a first scan line;
a third transistor, the third transistor comprising a third gate electrode which is a portion of a second scan line; and
a conductive pattern physically connected to the first gate electrode,
wherein the conductive pattern overlaps the first scan line and the second scan line in a plan view.
17. The display device of claim 16 , wherein the second transistor is a PMOS transistor, and the third transistor is a NMOS transistor.
18. The display device of claim 16 , wherein an overlapping area of the conductive pattern and the first scan line is larger than the overlapping area of the conductive pattern and the second scan line.
19. The display device of claim 16 , further comprising a substrate,
wherein the first scan line, the second scan line, the conductive pattern and the light-emitting diode are sequentially disposed on the substrate.
20. The display device of claim 19 , further comprising:
a first semiconductor layer disposed on the substrate, the first semiconductor layer comprising a second channel region of the second transistor overlapping the second gate electrode in the plan view; and
a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising a third channel region of the third transistor overlapping the third gate electrode in the plan view, wherein the third channel region is farther than the second channel region from the substrate.
21. The display device of claim 20 , further comprising a first supply voltage line electrically connected to the first electrode, wherein:
the first supply voltage line is disposed on the conductive pattern; and
the first supply voltage line is overlapped with the third channel region in the plan view.