Series capacitor buck converter and controller circuit and control method thereof

1. A controller circuit of a series capacitor buck converter,

the series capacitor buck converter including

an input line and an output line,

a first switch having a first end connected to the input line,

a coupled inductor including a first inductor and a second inductor, each of the first inductor and the second inductor having a first end connected to the output line,

a second switch connected between a first switching node which is a second end of the first inductor, and a ground,

a series capacitor connected between a second end of the first switch and the first switching node,

a third switch connected between the second end of the first switch and a second switching node which is a second end of the second inductor,

a fourth switch connected between the second switching node and the ground, and

an output capacitor connected to the output line,

the controller circuit comprising:

a control logic circuit that generates a plurality of control signals instructing ON-OFF states of the first to fourth switches so as to alternately repeat a first state in which the first switch and the fourth switch are ON and a second state in which the second switch and the third switch are ON, with an interval of dead time; and

a first timing generator that generates a first timing signal as a trigger for turning on the first switch at a second dead time inserted into a period of transition from the second state to the first state, wherein

the first timing generator changes timing of assertion of the first timing signal so as to bring timing at which the first switch is actually turned on and timing at which a first switching voltage generated in the first switching node crosses a predetermined upper threshold closer to each other at the second dead time.

2. The controller circuit according to claim 1 , wherein

the first timing generator includes

a first delay circuit that asserts the first timing signal after a variable delay time elapses from a shift to the second dead time,

a first turn-on detection circuit that compares a gate voltage of the first switch with a threshold and that generates a first ON detection signal asserted when the first switch is actually turned on,

a first high transition detection circuit that asserts a first high transition detection signal when the first switching voltage crosses the upper threshold, and

a first delay adjustment circuit that adjusts the variable delay time of the first delay circuit to bring timing of the assertion of the first ON detection signal and timing of the assertion of the first high transition detection signal closer to each other.

3. The controller circuit according to claim 1 , wherein

the first timing generator includes

a first delay circuit that asserts the first timing signal after a variable delay time elapses from a shift to the second dead time,

a first turn-on detection circuit that compares a gate voltage of the first switch with a threshold and that generates a first ON detection signal asserted when the first switch is actually turned on,

a sample and hold circuit that samples and holds the first switching voltage in response to the assertion of the first ON detection signal, and

a first delay adjustment circuit that adjusts the variable delay time of the first delay circuit on a basis of a comparison result of an output of the sample and hold circuit and the upper threshold.

4. The controller circuit according to claim 1 , further comprising:

a third timing generator that generates a third timing signal as a trigger for turning on the third switch at a first dead time inserted into a period of transition from the first state to the second state, wherein

the third timing generator changes timing of assertion of the third timing signal to bring timing at which the third switch is actually turned on and timing at which a second switching voltage generated in the second switching node crosses a predetermined upper threshold closer to each other at the first dead time.

5. The controller circuit according to claim 4 , wherein

a configuration of the third timing generator is same as a configuration of the first timing generator.

6. The controller circuit according to claim 1 , further comprising:

a third timing generator that generates a third timing signal as a trigger for turning on the third switch at a first dead time inserted into a period of transition from the first state to the second state, wherein

the third timing generator generates the third timing signal by copying information for generating the first timing signal generated by the first timing generator.

7. The controller circuit according to claim 1 , further comprising:

a second timing generator that generates a second timing signal as a trigger for turning on the second switch at a first dead time inserted into a period of transition from the first state to the second state, wherein

the second timing generator changes timing of assertion of the second timing signal to bring timing at which the second switch is actually turned on and timing at which a second switching voltage generated in the second switching node crosses a predetermined lower threshold closer to each other at the first dead time.

8. The controller circuit according to claim 7 , wherein

the second timing generator includes

a second turn-on detection circuit that compares a gate voltage of the second switch with a threshold and that generates a second ON detection signal asserted when the second switch is actually turned on,

a first low transition detection circuit that asserts a first low transition detection signal when the first switching voltage crosses the lower threshold,

a second delay circuit that asserts the second timing signal after a variable delay time elapses from a shift to the first dead time, and

a second delay adjustment circuit that adjusts the variable delay time of the second delay circuit to bring timing of the assertion of the second ON detection signal and timing of the assertion of the first low transition detection signal closer to each other.

9. The controller circuit according to claim 7 , wherein

the second timing generator includes

a second delay circuit that asserts the second timing signal after a variable delay time elapses from a shift to the first dead time,

a second turn-on detection circuit that compares a gate voltage of the second switch with a threshold and that generates a second ON detection signal asserted when the second switch is actually turned on,

a sample and hold circuit that samples and holds the first switching voltage in response to the assertion of the second ON detection signal, and

a second delay adjustment circuit that adjusts the variable delay time of the second delay circuit on a basis of a comparison result of an output of the sample and hold circuit and the lower threshold.

10. The controller circuit according to claim 7 , further comprising:

a fourth timing generator that generates a fourth timing signal as a trigger for turning on the fourth switch at the second dead time inserted into the period of transition from the second state to the first state, wherein

the fourth timing generator changes timing of assertion of the fourth timing signal to bring timing at which the fourth switch is actually turned on and timing at which the first switching voltage crosses the predetermined lower threshold closer to each other at the second dead time.

11. The controller circuit according to claim 10 , wherein

a configuration of the fourth timing generator is same as a configuration of the second timing generator.

12. The controller circuit according to claim 10 , further comprising:

a fourth timing generator that generates a fourth timing signal as a trigger for turning on the fourth switch at the second dead time inserted into the period of transition from the second state to the first state, wherein

the fourth timing generator generates the fourth timing signal by copying information for generating the second timing signal generated by the second timing generator.

13. The controller circuit according to claim 1 , the controller circuit being integrated into one semiconductor substrate.

14. A series capacitor buck converter comprising:

a main circuit of the series capacitor buck converter; and

the controller circuit according to claim 1 , the controller circuit driving the main circuit.

15. A controller circuit of a series capacitor buck converter,

the series capacitor buck converter including

an input line and an output line,

a first switch having a first end connected to the input line,

a coupled inductor including a first inductor and a second inductor, each of the first inductor and the second inductor having a first end connected to the output line,

a second switch connected between a first switching node which is a second end of the first inductor, and a ground,

a series capacitor connected between a second end of the first switch and the first switching node,

a third switch connected between the second end of the first switch and a second switching node which is a second end of the second inductor,

a fourth switch connected between the second switching node and the ground, and

an output capacitor connected to the output line,

the controller circuit comprising:

a control logic circuit that generates a plurality of control signals instructing ON-OFF states of the first to fourth switches so as to alternately repeat a first state in which the first switch and the fourth switch are ON and a second state in which the second switch and the third switch are ON, with an interval of dead time; and

a third timing generator that generates a third timing signal as a trigger for turning on the third switch at a first dead time inserted into a period of transition from the first state to the second state, wherein

the third timing generator changes timing of assertion of the third timing signal so as to bring timing at which the third switch is actually turned on and timing at which a second switching voltage generated in the second switching node crosses a predetermined upper threshold closer to each other at the first dead time.

16. A control method of a series capacitor buck converter,

the series capacitor buck converter including

an input line and an output line,

a first switch including a first end connected to the input line,

a coupled inductor including a first inductor and a second inductor, each of the first inductor and the second inductor having a first end connected to the output line,

a second switch connected between a first switching node which is a second end of the first inductor, and a ground,

a series capacitor connected between a second end of the first switch and the first switching node,

a third switch connected between the second end of the first switch and a second switching node which is a second end of the second inductor,

a fourth switch connected between the second switching node and the ground, and

an output capacitor connected to the output line,

the control method comprising:

alternately repeating a first state in which the first switch and the fourth switch are ON and a second state in which the second switch and the third switch are ON, with an interval of dead time; and

adjusting timing of a first timing signal, which is a trigger for turning on the first switch, so as to bring timing at which the first switch is actually turned on and timing at which a first switching voltage generated in the first switching node crosses a predetermined upper threshold closer to each other at a second dead time inserted into a period of transition from the second state to the first state.