Quasi co-location (QCL) prioritization rules for multi-transmission configuration indicator (TCI) state control resource set (CORESET)
A method of wireless communication performed by a user equipment (UE) includes receiving a message indicating multiple control resource sets (CORESETs). Each CORESET of the multiple CORESETs comprising one or more quasi-co-location (QCL)-Type-D properties and associated with a respective physical downlink control (PDCCH) monitoring occasion of overlapping PDCCH monitoring occasions. One or more respective PDCCH candidates corresponding to the respective PDCCH monitoring occasion. The method also includes receiving, on one or more component carriers (CCs) operating on a same band, simultaneous beams comprising multiple PDCCH candidates. The method further includes monitoring a set of PDCCH candidates of the plurality of PDCCH candidates comprising a first CORESET of the multiple CORESETs comprising a first QCL-Type-D property, a second CORESET of the multiple CORESETs associated with a second QCL-Type-D property, and a set of monitoring CORESETs of the multiple CORESETs. Each of the monitoring CORESET associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of a respective monitoring CORESET. In some examples, the first CORESET is a highest priority CORESET based on a set of priority rules.
1. A user equipment (UE), comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to cause the UE to:
receive a message indicating a plurality of CORESETs, wherein each CORESET of the plurality of CORESETs comprises one or more quasi-co-location (QCL)-Type-D properties and is associated with a respective physical downlink control channel (PDCCH) monitoring occasion of a plurality of overlapping PDCCH monitoring occasions, and wherein one or more respective PDCCH candidates correspond to the respective PDCCH monitoring occasion;
receive, on one or more component carriers (CCs) in a same band, a plurality of simultaneous beams comprising a plurality of PDCCH candidates;
exclude, from the plurality of CORESETs, each CORESET comprising a single QCL-Type-D property based on one or more CORESETs of the plurality of CORESETs comprising two QCL-Type-D properties;
prioritize the plurality of CORESETs after excluding each CORESET comprising the single QCL-Type-D property; and
monitor a set of PDCCH candidates of the plurality of PDCCH candidates associated with: a first CORESET of the plurality of CORESETs comprising a first QCL-Type-D property, a second CORESET of the plurality of CORESETs comprising a second QCL-Type-D property, and a set of monitoring CORESETs of the plurality of CORESETs each associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of the respective monitoring CORESET, wherein the first CORESET is a highest priority CORESET based on a set of priority rules.
2. The UE of claim 1 , wherein:
the first CORESET comprises only the first QCL-Type-D property; or
the first CORESET comprises the two QCL-Type-D properties and the first QCL-Type-D property comprises a first primary QCL-Type-D property of the two QCL-Type-D properties.
3. The UE of claim 2 , wherein:
a secondary QCL-Type-D property of the first CORESET comprises the second QCL-Type-D property based on the first CORESET comprising the two QCL-Type-D properties; and
the first CORESET is a same CORESET as the second CORESET.
4. The UE of claim 1 , wherein:
the set of priority rules comprise one or more of: prioritize in order of a search space (SS) type, prioritize in order of a serving cell index, or prioritize in order of an SS set index; and
the search space type comprises a common search space (CSS) and a UE-specific search space (USS).
5. The UE of claim 1 , wherein each QCL-Type-D property is associated with a receive beam property.
6. A user equipment (UE), comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to cause the UE to:
receive a message indicating a plurality of CORESETs, wherein each CORESET of the plurality of CORESETs comprises one or more quasi-co-location (QCL)-Type-D properties and is associated with a respective physical downlink control channel (PDCCH) monitoring occasion of a plurality of overlapping PDCCH monitoring occasions, and wherein one or more respective PDCCH candidates correspond to the respective PDCCH monitoring occasion;
receive, on one or more component carriers (CCs) in a same band, a plurality of simultaneous beams comprising a plurality of PDCCH candidates;
monitor a set of PDCCH candidates of the plurality of PDCCH candidates associated with: a first CORESET of the plurality of CORESETs comprising a first QCL-Type-D property, a second CORESET of the plurality of CORESETs comprising a second QCL-Type-D property, and a set of monitoring CORESETs of the plurality of CORESETs each associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of the respective monitoring CORESET, wherein the first CORESET is a highest priority CORESET based on a set of priority rules;
exclude the first CORESET from a prioritized plurality of CORESETs; and
exclude, from the prioritized plurality of CORESETs, a first set of CORESETs based on each CORESET in the first set of CORESETs comprising a single QCL-Type-D property,
wherein the single QCL-Type-D property of each CORESET in the first set of CORESETs is equal to the first QCL-Type-D property.
7. The UE of claim 6 , wherein the processor is configured to cause the UE to exclude, from the prioritized plurality of CORESETs, a second set of CORESETs based on:
each CORESET in the second set of CORESETs comprising two QCL-Type-D properties, and
each one of the two QCL-Type-D properties being different from the first QCL-Type-D property.
8. The UE of claim 7 , wherein the second CORESET is a second highest priority CORESET in the second set of CORESETs based on the prioritized plurality of CORESETs being empty after excluding the first set of CORESETs and the second set of CORESETs.
9. The UE of claim 7 , wherein the processor is configured to cause the UE to select the second CORESET from the prioritized plurality of CORESETs after excluding the first set of CORESETs and the second set of CORESETs.
10. The UE of claim 9 , wherein the processor is configured to cause the UE to:
select the second CORESET based on the second CORESET being a second highest priority CORESET in the prioritized plurality of CORESETs; or
select the second CORESET based one or more of a search space (SS) type, a serving cell index, or an SS set index of the first CORESET.
11. The UE of claim 9 , wherein the processor is configured to cause the UE to:
exclude the second set of CORESETs prior to excluding the first set of CORESETs, and
select the first CORESET after excluding the second set of CORESETs and prior to excluding the first set of CORESETs.
12. The UE of claim 6 , wherein the processor is configured to cause the UE to:
exclude, from the prioritized plurality of CORESETs, a second set of CORESETs based on each CORESET in the second set of CORESETs comprising two QCL-Type-D properties, and each secondary QCL-Type-D property of each CORESET in the second set of CORESETs being equal to the first QCL-Type-D property; and
select the second CORESET from the prioritized plurality of CORESETs after excluding the first set of CORESETs, wherein:
the second CORESET comprises only the second QCL-Type-D property; or
the second QCL-Type-D property is a secondary QCL-Type-D property of two QCL-Type-D properties of the second CORESET when the second CORESET comprises the two QCL-Type-D properties.
13. The UE of claim 6 , wherein each QCL-Type-D property is associated with a receive beam property.
14. The UE of claim 6 , wherein the first CORESET comprises only the first QCL-Type-D property.
15. The UE of claim 6 , wherein the first CORESET comprises two QCL-Type-D properties, and wherein the first QCL-Type-D property comprises a first primary QCL-Type-D property of the two QCL-Type-D properties.
16. A user equipment (UE), comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to cause the UE to:
receive a message indicating a plurality of CORESETs, wherein each CORESET of the plurality of CORESETs comprises one or more quasi-co-location (QCL)-Type-D properties and is associated with a respective physical downlink control channel (PDCCH) monitoring occasion of a plurality of overlapping PDCCH monitoring occasions, and wherein one or more respective PDCCH candidates correspond to the respective PDCCH monitoring occasion;
receive, on one or more component carriers (CCs) in a same band, a plurality of simultaneous beams comprising a plurality of PDCCH candidates;
monitor a set of PDCCH candidates of the plurality of PDCCH candidates associated with: a first CORESET of the plurality of CORESETs comprising a first QCL-Type-D property, a second CORESET of the plurality of CORESETs comprising a second QCL-Type-D property, and a set of monitoring CORESETs of the plurality of CORESETs each associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of the respective monitoring CORESET, wherein the first CORESET is a highest priority CORESET based on a set of priority rules;
identify a third CORESET comprising two QCL-Type-D properties, wherein a first QCL-Type-D property of the two QCL-Type-D properties of the third CORESET is equal to the first QCL-Type-D property or the second QCL-Type-D property, and wherein a second QCL-Type-D property of the two QCL-Type-D properties of the third CORESET is different from both the first QCL-Type-D property and the second QCL-Type-D property;
include, in the set of PDCCH candidates, a first PDCCH candidate from the plurality of PDCCH candidates corresponding to the first QCL-Type-D property of the third CORESET; and
exclude, from the set of PDCCH candidates, a second PDCCH candidate from the plurality of PDCCH candidates corresponding to the second QCL-Type-D property of the third CORESET.
17. The UE of claim 16 , wherein:
the first PDCCH candidate and the second PDCCH candidate are frequency division multiplexed; and
the processor is configured to cause the UE to monitor resource element groups (REGs) of the set of PDCCH candidates.
18. The UE of claim 16 , wherein:
the first PDCCH candidate and the second PDCCH candidate are space division multiplexed; and
the processor is configured to cause the UE to monitor beams of the set of PDCCH candidates.
19. The UE of claim 16 , wherein each QCL-Type-D property is associated with a receive beam property.
20. The UE of claim 16 , wherein the first PDCCH candidate and the second PDCCH candidate are frequency division multiplexed, and wherein, to monitor the set of PDCCH candidates, the processor is configured to cause the UE to monitor resource element groups (REGs) of the set of PDCCH candidates.
21. The UE of claim 16 , wherein the first PDCCH candidate and the second PDCCH candidate are space division multiplexed, and wherein, to monitor the set of PDCCH candidates, the processor is configured to cause the UE to monitor beams of the set of PDCCH candidates.
22. A user equipment (UE), comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to cause the UE to:
receive a message indicating a plurality of CORESETs, wherein each CORESET of the plurality of CORESETs comprises one or more quasi-co-location (QCL)-Type-D properties and is associated with a respective physical downlink control channel (PDCCH) monitoring occasion of a plurality of overlapping PDCCH monitoring occasions, and wherein one or more respective PDCCH candidates correspond to the respective PDCCH monitoring occasion;
receive, on one or more component carriers (CCs) in a same band, a plurality of simultaneous beams comprising a plurality of PDCCH candidates;
monitor a set of PDCCH candidates of the plurality of PDCCH candidates associated with: a first CORESET of the plurality of CORESETs comprising a first QCL- Type-D property, a second CORESET of the plurality of CORESETs comprising a second QCL-Type-D property, and a set of monitoring CORESETs of the plurality of CORESETs each associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of the respective monitoring CORESET, wherein the first CORESET is a highest priority CORESET based on a set of priority rules;
exclude the first CORESET and the second CORESET from a prioritized plurality of CORESETs;
identify, from the prioritized plurality of CORESETs after excluding the first CORESET and the second CORESET, a first set of CORESETs based on each CORESET of the first set of CORESETs comprising a single QCL-Type-D property being the same as the first QCL-Type-D property or the second QCL-Type-D property;
identify, from the prioritized plurality of CORESETs, a second set of CORESETs, based on each CORESET of the second set of CORESETs comprising two QCL-Type- D properties, wherein a primary QCL-Type-D property of each CORESET of the second set of CORESETs is the same as the first QCL-Type-D property, and wherein a secondary QCL-Type-D property of each CORESET of the second set of CORESETs is the same as the second QCL-Type-D property; and
identify the first set of CORESETs and the second set of CORESETs as the set of monitoring CORESETs.
23. The UE of claim 22 , wherein each QCL-Type-D property is associated with a receive beam property.