IP Library › Granted Patent US 12,433,056
Granted Patent B2
US 12,433,056 · App. 17/555,670 · Granted Sep 30, 2025

Planar germanium photodetector

Inventors: Wei Qian (Walnut, CA); Zhi Li (San Jose, CA)
Assignee: Intel Corporation
H10F77/122H10F30/2235H10F71/121H10F71/1212H10F77/147H10F77/1662H10F39/103
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Quick Facts
Patent No.
US 12,433,056
App. No.
17/555,670
Granted
Sep 30, 2025
Kind
B2
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques directed to a planar germanium photodetector that includes n-type and p-type amorphous silicon deposits on a germanium slab. During operation, a uniform electrical field is formed across the germanium bulk between the amorphous silicon deposits. Other embodiments may be described and/or claimed.

Claims (46)

1. A photodetector comprising:

a substrate;

a germanium layer on top of the substrate; and

an n-type silicon layer at least partially within the germanium layer and a p-type silicon layer at least partially within the germanium layer, wherein a portion of the germanium layer between the n-type silicon layer and the p-type silicon layer isolates the n-type silicon layer and the p-type silicon layer from each other, the n-type silicon layer having an uppermost surface at a same level as an uppermost surface of the germanium layer, and the p-type silicon layer having an uppermost surface at a same level as the uppermost surface of the germanium layer.

2. The photodetector of claim 1 , wherein the portion of the germanium layer between the n-type silicon layer and the p-type silicon layer is a first portion; and further comprising second portion of the germanium layer that separates the n-type silicon layer and the p-type silicon layer from the substrate.

3. The photodetector of claim 1 , wherein the n-type silicon layer is an amorphous silicon layer, and wherein the p-type silicon layer is an amorphous silicon layer.

4. The photodetector of claim 1 , further comprising a waveguide optically coupled with the portion of the germanium layer between the n-type silicon layer and the p-type silicon layer.

5. The photodetector of claim 4 , wherein the waveguide is a silicon waveguide.

6. The photodetector of claim 1 , wherein, during operation of the photo detector, current flows from the n-type silicon layer to the p-type silicon layer through the portion of the germanium layer.

7. The photodetector of claim 1 , wherein, during operation of the photodetector, an electric field forms within the portion of the germanium layer, wherein the formed electric field is substantially uniform.

8. The photodetector of claim 1 , wherein a thickness of the n-type silicon layer and a thickness of the p-type silicon layer ranges from 0.1 μm to 0.2 μm.

9. The photodetector of claim 1 , wherein a minimum distance between the n-type silicon layer and the p-type silicon layer ranges from 0.2 μm to 0.6 μm.

10. The photodetector of claim 1 , wherein an edge plane of the n-type silicon layer proximate to the p-type silicon layer, and an edge plane of the p-type silicon layer proximate to the n-type silicon layer are substantially parallel.

11. The photodetector of claim 1 , further comprising a first electrical contact electrically coupled with the n-type layer of silicon and a second electrical contact electrically coupled with the p-type layer of silicon.

12. The photodetector of claim 11 , wherein the first electrical contact and the second electrical contact are within a metal layer.

13. The photodetector of claim 1 , wherein the substrate is a silicon substrate.

14. The photodetector of claim 1 , wherein the substrate is on a buried oxide (BOX) layer.

15. A method comprising:

providing a layer that includes silicon;

forming a layer that includes germanium on a side of the layer that includes silicon;

forming an n-type layer of silicon within the layer that includes germanium, the n-type layer of silicon having an uppermost surface at a same level as an uppermost surface of the layer that incudes germanium; and

forming a p-type layer of silicon within the layer that includes germanium, the p-type layer of silicon having an uppermost surface at a same level as the uppermost surface of the layer that includes germanium, wherein a portion of the layer that includes germanium isolates the n-type layer of silicon and the p-type layer of silicon.

16. The method of claim 15 , wherein the n-type layer of silicon and the p-type layer of silicon are separated from the layer that includes silicon by a portion of the layer that includes germanium.

17. The method of claim 15 , wherein the n-type silicon layer is an amorphous silicon layer, and wherein the p-type silicon layer is an amorphous silicon layer.

18. The method of claim 15 , wherein forming the n-type layer of silicon further includes:

etching a first cavity within the layer of germanium; and

forming the n-type layer of silicon within the first cavity; and

wherein forming the p-type layer of silicon further includes:

etching a second cavity within the layer of germanium; and

forming the p-type layer of silicon within the second cavity.

19. The method of claim 15 , further comprising:

forming a first metal conductor on the n-type layer of silicon; and

forming a second metal conductor on the p-type layer of silicon.

20. The method of claim 15 , wherein a thickness of the n-type layer of silicon and a thickness of the p-type layer of silicon ranges from 0.1 μm to 0.3 μm, or wherein a minimum distance between the n-type layer of silicon and the p-type layer of silicon ranges from 0.2 μm to 0.6 μm.

21. A package comprising:

a photodetector comprising:

a silicon substrate;

a germanium layer on top of the silicon substrate;

an n-type amorphous silicon layer at least partially within the germanium layer and a p-type amorphous silicon layer at least partially within the germanium layer, wherein a portion of the germanium layer between the n-type amorphous silicon layer and the p-type amorphous silicon layer isolates the n-type amorphous silicon layer and the p-type amorphous silicon layer from each other, the n-type silicon layer having an uppermost surface at a same level as an uppermost surface of the germanium layer, and the p-type silicon layer having an uppermost surface at a same level as the uppermost surface of the germanium layer, and wherein the n-type amorphous silicon layer and the p-type amorphous silicon layer are within a plane;

a first electrical contact electrically coupled with the n-type amorphous silicon layer; and

a second electrical contact electrically coupled with the p-type amorphous silicon layer; and

an electrical component electrically coupled with the first electrical contact and the second electrical contact.

22. The package of claim 21 , further comprising a waveguide optically coupled with the portion of the germanium layer between the n-type amorphous silicon layer and the p-type amorphous silicon layer.

23. The package of claim 21 , wherein the electrical component includes a selected one of: a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), or memory.

24. The package of claim 21 , wherein during operation of the photodetector, an electric field forms within the portion of the germanium layer, wherein the formed electric field is substantially uniform.

25. The package of claim 21 , wherein the photodetector is a plurality of photo detectors, and wherein the electrical component is a plurality of electrical components.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2022
From: QIAN, WEI; LI, ZHI
To: INTEL CORPORATION
Reel/Frame 060875/0311 →
Continuity (1)
Related Publication 20230197867A1 · Jun 22, 2023
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