Device of measuring duty cycle and compensation circuit utilizing the same
A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.
1. A compensation circuit comprising:
a resistor-capacitor circuit configured to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state, the resistor-capacitor circuit comprising:
a first resistor-capacitor sub-circuit comprising:
a first path comprising a first resistor;
a second path comprising a second resistor; and
a first storage capacitor shared by the first path and the second path, wherein the first storage capacitor is charged via the first path, or discharged via the second path; and
a second resistor-capacitor sub-circuit, wherein the first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit operate simultaneously to compute an ON time of a front end module; and
a control circuit coupled to the resistor-capacitor circuit, and configured to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and comprising an adjustment circuit configured to generate a bias signal according to the ON time, and output the bias signal to the front end module.
2. The compensation circuit of claim 1 , wherein the front end module is an amplifier comprising N amplification stages, and N is a positive integer; and
the adjustment circuit outputs the bias signal to a first amplification stage of the N amplification stages.
3. The compensation circuit of claim 1 , wherein the bias signal and the ON time are positively correlated.
4. The compensation circuit of claim 1 , wherein:
when the reference signal is in the first state, the reference signal charges the first storage capacitor via the first path; and
when the reference signal is in the second state, the first storage capacitor is configured to be discharged via the second path.
5. The compensation circuit of claim 1 , wherein:
the first resistor-capacitor sub-circuit is configured to generate the second voltage after the reference signal is in the second state for an OFF time; and
the second resistor-capacitor sub-circuit is configured to generate the third voltage after the reference signal is in the second state for the OFF time.
6. A compensation circuit comprising:
a resistor-capacitor circuit configured to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state, the resistor-capacitor circuit comprising:
a first resistor circuit comprising a first terminal configured to receive the reference voltage, and a second terminal;
a second resistor circuit comprising a first terminal, and a second terminal coupled to a ground terminal and configured to selectively provide a first resistance or a second resistance; and
a storage capacitor circuit comprising a first terminal selectively coupled to the second terminal of the first resistor circuit or the first terminal of the second resistor circuit, and a second terminal coupled to the ground terminal; and
a control circuit coupled to the resistor-capacitor circuit, and configured to acquire an ON time of a front end module according to the first voltage, the second voltage, and the third voltage, and comprising an adjustment circuit configured to generate a bias signal according to the ON time, and output the bias signal to the front end module;
wherein in a first period, the second resistor circuit provides the first resistance, and after the first period has elapsed, the first terminal of the storage capacitor circuit generates the second voltage;
in a second period, the second resistor circuit provides the second resistance, and after the second period has elapsed, the first terminal of the storage capacitor circuit generates the third voltage; and
the first resistor circuit is configured to charge the storage capacitor circuit, and the second resistor circuit is configured to discharge the storage capacitor circuit.
7. The compensation circuit of claim 6 , wherein the front end module is an amplifier comprising N amplification stages, and N is a positive integer; and
the adjustment circuit outputs the bias signal to a first amplification stage of the N amplification stages.
8. The compensation circuit of claim 6 , wherein the bias signal and the ON time are positively correlated.
9. The compensation circuit of claim 6 , wherein the second resistor circuit is a variable resistor.
10. The compensation circuit of claim 6 , wherein the second resistor circuit comprises:
a first resistor comprising a first terminal, and a second terminal coupled to the ground terminal, and having a first resistance, and
a second resistor comprising a first terminal, and a second terminal coupled to the ground terminal, and having a second resistance; and
a switch comprising a first terminal coupled to the first terminal of the second resistor circuit, a second terminal selectively coupled to the first terminal of the first resistor or the first terminal of the second resistor.
11. The compensation circuit of claim 6 , wherein the storage capacitor circuit comprises:
a first capacitor comprising a first terminal, and a second terminal coupled to the ground terminal, and having a first capacitance; and
a second capacitor comprising a first terminal, and a second terminal coupled to the ground terminal, and having a second capacitance; and
a switch comprising a first terminal coupled to the first terminal of the storage capacitor circuit, a second terminal selectively coupled to the first terminal of the first capacitor or the first terminal of the second capacitor.
12. A compensation circuit comprising:
a resistor-capacitor circuit configured to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state; and
a control circuit coupled to the resistor-capacitor circuit, and configured to acquire an ON time of a front end module according to the first voltage, the second voltage, and the third voltage, and comprising:
an adjustment circuit configured to adjust an input impedance and/or output impedance of the front end module according to the ON time, generate a bias signal according to the ON time, and output the bias signal to the front end module, the adjustment circuit comprising:
a bias current source configured to generate a first bias current and a second bias current; and
a switch coupled to the bias current source and configured to provide the bias signal based on the first bias current and the second bias current.
13. The compensation circuit of claim 12 , wherein the adjustment circuit is further configured to generate an adjustment signal according to the ON time, and adjust the input impedance and/or output impedance of the front end module according to the adjustment signal.
14. The compensation circuit of claim 13 , wherein the adjustment circuit is further configured to generate the bias signal according to the adjustment signal.
15. The compensation circuit of claim 12 , wherein the front end module is an amplifier comprising N amplification stages, and N is a positive integer; and
the adjustment circuit outputs the bias signal to a first amplification stage of the N amplification stages.
16. The compensation circuit of claim 12 , wherein the bias signal and the ON time are positively correlated.
17. The compensation circuit of claim 12 , wherein the control circuit acquires the ON time from a look-up table according to the first voltage, the second voltage and the third voltage.
18. The compensation circuit of claim 12 , wherein the front end module is an amplifier circuit.