IP Library › Granted Patent US 12,436,431
Granted Patent B2
US 12,436,431 · App. 18/211,623 · Granted Oct 7, 2025

Display device, module, and electronic device

Inventors: Shuhei Yoshitomi (Kanagawa, JP); Daisuke Kubota (Kanagawa, JP); Koji Kusunoki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/134309G02F1/1368G06F1/3265G06F3/044G06F3/0446G02F1/134345G02F1/134372G02F1/136286G02F2201/121G02F2201/123G02F2201/40Y02D10/00
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Quick Facts
Patent No.
US 12,436,431
App. No.
18/211,623
Granted
Oct 7, 2025
Kind
B2
Abstract

A high-definition liquid crystal display device is provided. A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with a high contrast ratio and display quality is provided. A liquid crystal display device capable of being driven at a low voltage is provided. The display device includes, between a pair of substrates, a pixel electrode, a first common electrode, a second common electrode, and a liquid crystal layer. The pixel electrode and the first common electrode are positioned between the liquid crystal layer and one of the substrates. The second common electrode is positioned between the liquid crystal layer and the other substrate. The same potential is supplied to the first common electrode and the second common electrode. The first common electrode includes a portion overlapping with the second common electrode between the display regions of two adjacent subpixels that exhibit different colors. At least one of the pixel electrode and the first common electrode includes a portion that does not overlap with the second common electrode in the display region of the subpixel.

Claims (19)

1. A liquid crystal display device comprising a first pixel and a second pixel,

wherein the liquid crystal display device comprises a first common electrode, a second common electrode, an auxiliary wiring, a light-blocking layer, and a liquid crystal layer,

wherein the first pixel comprises a first transistor and a first pixel electrode,

wherein the second pixel comprises a second transistor and a second pixel electrode,

wherein the first common electrode, the auxiliary wiring, the first transistor, and the second transistor are provided over a first substrate,

wherein, in a cross-sectional view of the liquid crystal display device, the first common electrode is positioned between the first transistor and the liquid crystal layer,

wherein in a top view of the liquid crystal display device, the first common electrode overlaps with the first pixel and the second pixel,

wherein in a top view of the liquid crystal display device, the first common electrode comprises a first opening and a second opening,

wherein in a top view of the liquid crystal display device, the first opening comprises a first region which the first transistor is in contact with the first pixel electrode,

wherein in a top view of the liquid crystal display device, the second opening comprises a second region which the second transistor is in contact with the second pixel electrode,

wherein the first common electrode is in contact with the auxiliary wiring at a third region,

wherein the second common electrode overlaps with the first common electrode, the first pixel electrode, and the second pixel electrode,

wherein the second common electrode includes a third opening,

wherein, in a cross-sectional view of the liquid crystal display device, the third opening overlaps with a region which is not provided with the first pixel electrode, and

wherein the third region overlaps with the light-blocking layer.

2. The liquid crystal display device according to claim 1 , wherein the resistivity of the auxiliary wiring is lower than the resistivity of the first common electrode.

3. The liquid crystal display device according to claim 1 ,

wherein the liquid crystal display device comprises a driver circuit portion, and

wherein in a top view of the liquid crystal display device, the third region is positioned near the driver circuit portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: YOSHITOMI, SHUHEI; KUBOTA, DAISUKE; KUSUNOKI, KOJI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 063991/0205 →
Priority Claims (2)
JP 2016-050824 · Mar 15, 2016 · national
JP 2016-101543 · May 20, 2016 · national
Continuity (3)
Continuation 16780980 · Feb 4, 2020
Continuation 15455244 · Mar 10, 2017
Related Publication 20230341730A1 · Oct 26, 2023
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