IP Library Granted Patent US 12,436,702
Granted Patent B2
US 12,436,702 · App. 18/071,325 · Granted Oct 7, 2025

Hybrid wear leveling for in-place data replacement media

Inventors: Ying Yu Tai (Mountain View, CA); Jiangli Zhu (San Jose, CA); Ning Chen (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F3/0647G06F3/0616G06F3/0659G06F3/0673
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,436,702
App. No.
18/071,325
Granted
Oct 7, 2025
Kind
B2
Abstract

A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.

Claims (46)

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

periodically performing a first wear leveling operation using a direct mapping function on a data management unit of the memory device at a first frequency; and

periodically performing a second wear leveling operation using indirect mapping on groups of data management units of the memory device at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation, and wherein periodically performing the second wear leveling operation comprises:

detecting an occurrence of a trigger corresponding to the second wear leveling operation:

identifying an available physical location of a plurality of physical locations on the memory device, wherein the available physical location is identified based on respective write counts of the plurality of physical locations on the memory device;

copying data from one of the groups of data management units to the available physical location; and

updating an entry in a look-up table, the entry corresponding to a logical index associated with the data from the one of the groups of data management units and indicating a physical index corresponding to the available physical location.

2. The system of claim 1 , wherein the memory device comprises a cross-point array of non-volatile memory cells.

3. The system of claim 1 , wherein periodically performing the first wear leveling operation using the direct mapping function comprises:

applying a first logical index associated with data from the data management unit to the direct mapping function to determine a physical index corresponding to a physical location on the memory device; and

copying the data from the data management unit to the physical location.

4. The system of claim 3 , wherein the direct mapping function comprises a swap function.

5. The system of claim 3 , wherein the direct mapping function comprises a circular shift function.

6. The system of claim 3 , wherein the direct mapping function comprises a linear function utilizing a base pointer value and a free pointer value.

7. The system of claim 1 , wherein the first frequency and the second frequency are based on a period of time that has elapsed since a previous wear leveling operation was performed.

8. The system of claim 1 , wherein the first frequency and the second frequency are based on a number of data write operations performed on the memory device by a host machine since a previous wear leveling operation was performed.

9. A method comprising:

periodically performing a first wear leveling operation using a direct mapping function on a data management unit of a memory device at a first frequency; and

periodically performing a second wear leveling operation using indirect mapping on groups of data management units of the memory device at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation, and wherein periodically performing the second wear leveling operation comprises:

detecting an occurrence of a trigger corresponding to the second wear leveling operation;

identifying an available physical location of a plurality of physical locations on the memory device, wherein the available physical location is identified based on respective write counts of the plurality of physical locations on the memory device;

copying data from one of the groups of data management units to the available physical location; and

updating an entry in a look-up table, the entry corresponding to a logical index associated with the data from the one of the groups of data management units and indicating a physical index corresponding to the available physical location.

10. The method of claim 9 , wherein the memory device comprises a cross-point array of non-volatile memory cells.

11. The method of claim 9 , wherein periodically performing the first wear leveling operation using the direct mapping function comprises:

applying a first logical index associated with data from the data management unit to the direct mapping function to determine a physical index corresponding to a physical location on the memory device; and

copying the data from the data management unit to the physical location.

12. The method of claim 11 , wherein the direct mapping function comprises a swap function.

13. The method of claim 11 , wherein the direct mapping function comprises a circular shift function.

14. The method of claim 11 , wherein the direct mapping function comprises a linear function utilizing a base pointer value and a free pointer value.

15. The method of claim 9 , wherein the first frequency and the second frequency are based on a period of time that has elapsed since a previous wear leveling operation was performed.

16. The method of claim 9 , wherein the first frequency and the second frequency are based on a number of data write operations performed on the memory device by a host machine since a previous wear leveling operation was performed.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

periodically performing a first wear leveling operation using a direct mapping function on a data management unit of a memory device at a first frequency; and

periodically performing a second wear leveling operation using indirect mapping on groups of data management units of the memory device at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation, and wherein periodically performing the second wear leveling operation comprises:

detecting an occurrence of a trigger corresponding to the second wear leveling operation;

identifying an available physical location of a plurality of physical locations on the memory device, wherein the available physical location is identified based on respective write counts of the plurality of physical locations on the memory device;

copying data from one of the groups of data management units to the available physical location; and

updating an entry in a look-up table, the entry corresponding to a logical index associated with the data from the one of the groups of data management units and indicating a physical index corresponding to the available physical location.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the memory device comprises a cross-point array of non-volatile memory cells.

19. The non-transitory computer-readable storage medium of claim 17 , wherein periodically performing the first wear leveling operation using the direct mapping function comprises:

applying a first logical index associated with data from the data management unit to the direct mapping function to determine a physical index corresponding to a physical location on the memory device; and

copying the data from the data management unit to the physical location.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the first frequency and the second frequency are based on at least one of a period of time that has elapsed since a previous wear leveling operation was performed or a number of data write operations performed on the memory device by a host machine since the previous wear leveling operation was performed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2022
From: TAI, YING YU; ZHU, JIANGLI; CHEN, NING
To: MICRON TECHNOLOGY, INC.
Reel/Frame 061912/0698 →
Continuity (2)
Continuation 16110691 · Aug 23, 2018
Related Publication 20230097187A1 · Mar 30, 2023
References Cited (61)
US 7756882B2 · Aharoni · 2010 [cited by applicant]
US 8364883B2 · Bennett · 2013 [cited by applicant]
US 8898373B1 · Kang · 2014 [cited by examiner]
US 9710176B1 · Tang · 2017 [cited by applicant]
US 10733110B1 · Volpe · 2020 [cited by examiner]
US 20040083335A1 · Gonzalez · 2004 [cited by examiner]
US 20050102523A1 · Harrison · 2005 [cited by applicant]
US 20080114785A1 · Bernstein · 2008 [cited by applicant]
US 20080140918A1 · Sutardja · 2008 [cited by applicant]
US 20080313505A1 · Lee · 2008 [cited by applicant]
US 20100017649A1 · Wu · 2010 [cited by applicant]
US 20100174845A1 · Gorobets · 2010 [cited by examiner]
US 20100185805A1 · Chen · 2010 [cited by applicant]
US 20100281202A1 · Abali · 2010 [cited by applicant]
US 20120253563A1 · Lobo · 2012 [cited by applicant]
US 20120278543A1 · Yu · 2012 [cited by applicant]
US 20120311228A1 · Hsu · 2012 [cited by applicant]
US 20120324141A1 · Seong · 2012 [cited by applicant]
US 20130054881A1 · Ellis · 2013 [cited by examiner]
US 20130138870A1 · Yoon · 2013 [cited by applicant]
US 20130166827A1 · Cideciyan · 2013 [cited by applicant]
US 20130304865A1 · Dewing · 2013 [cited by applicant]
US 20140063902A1 · Sunkavalli · 2014 [cited by applicant]
US 20140189284A1 · Hyuseinova · 2014 [cited by examiner]
US 20140237160A1 · Dong · 2014 [cited by applicant]
US 20150285919A1 · Lobo · 2015 [cited by applicant]
US 20150288847A1 · Sakuma · 2015 [cited by examiner]
US 20160211869A1 · Blaum · 2016 [cited by examiner]
US 20160378396A1 · Ramanujan · 2016 [cited by applicant]
US 20170177470A1 · Gunnam · 2017 [cited by applicant]
US 20170199769A1 · Jain · 2017 [cited by applicant]
US 20170242597A1 · Huang · 2017 [cited by applicant]
US 20170256305A1 · Niu · 2017 [cited by applicant]
US 20180004677A1 · Kim et al. · 2018 [cited by applicant]
US 20180060227A1 · Tang · 2018 [cited by examiner]
US 20180107386A1 · Ahn · 2018 [cited by examiner]
US 20180113636A1 · Kwon · 2018 [cited by applicant]
US 20190073136A1 · Chang · 2019 [cited by applicant]
US 20190107957A1 · Helmick · 2019 [cited by examiner]
US 20190108889A1 · Gholamipour · 2019 [cited by applicant]
US 20190370166A1 · Amato · 2019 [cited by applicant]
CN 1720590A · 2006 [cited by applicant]
CN 101558392A · 2009 [cited by applicant]
CN 102047230A · 2011 [cited by applicant]
CN 102047341A · 2011 [cited by applicant]
CN 103176752A · 2013 [cited by applicant]
CN 103765392A · 2014 [cited by applicant]
CN 106462500A · 2017 [cited by applicant]
EP 1713085A1 · 2006 [cited by applicant]
KR 20140017296A · 2014 [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2019/047425, mailed on Dec. 6, 2019, 11 pages. [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2019/047781, mailed Dec. 6, 2019, 10 pages. [cited by applicant]
R.T. Short and H. M. Levey, “A Simulation Study of Two-Level Caches”, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings, Honolulu, HI, USA, 1988, pp. 81-88. [cited by applicant]
“Layer Two Distribution and Load Balancing Techniques”, ip.com Prior Art Database Technical Disclosure, Feb. 2017. [cited by applicant]
Liu et al., “High Performance Memory Management for a Multi-core Architecture,” 2009 Ninth IEEE International Conference on Computer and Information Technology, 2009, pp. 63-68. [cited by applicant]
Bohnert et al., “A dynamic virtual memory management under real-time constraints,” 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014, pp. 1-10. [cited by applicant]
Balasa et al., “System-level exploration of hierarchical storage organizations for embedded data-intensive applications,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 638-641. [cited by applicant]
Huang et al., “Security RBSG: Protecting Phase Change Memory with Security-Level Adjustable Dynamic Mapping,” 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016, pp. 1081-1090. [cited by applicant]
Wang, et al., “An Alogrithm for Indirect Schema Mapping Composition,” 2009 First International Workshop on Education Technology and Computer Science, Wuhan, China, 2009, pp. 723-726. [cited by applicant]
Zhang et al., “An Algebraic Approach to Formal Analysis of Dynamic Software Updating Mechanisms,” 2012 19th Asia-Pacific Software Engineering Conference, Hong Kong, China, 2012, pp. 664-673. [cited by applicant]
Office Action for Chinese Patent Application No. 201980059927.3, mailed Jun. 25, 2024, 05 Pages. *Best available copy*. [cited by applicant]