IP Library Granted Patent US 12,436,813
Granted Patent B2
US 12,436,813 · App. 17/862,979 · Granted Oct 7, 2025

Memory disaggregation in a multi-node environment

Inventors: Yunfan Han (Austin, TX); Isaac Q. Wang (Austin, TX); Jordan Chin (Austin, TX)
Assignee: Dell Products L.P.
G06F9/5055G06F9/5044G06F9/5077
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Quick Facts
Patent No.
US 12,436,813
App. No.
17/862,979
Granted
Oct 7, 2025
Kind
B2
Abstract

An information handling system includes processing nodes, a compute express link (CXL) switch, and CXL devices. A workload orchestrator receives a workload to be instantiated on a particular one of the processing nodes, determines a set of resources associated with the workload, selects a particular one of the CXL devices to be used based upon the set or resources, and launches the workload on the processing node.

Claims (41)

1. An information handling system, comprising:

a plurality of processing nodes;

a compute express link (CXL) switch;

a plurality of CXL devices; and

a workload orchestrator configured to receive a first workload to be instantiated on a first one of the processing nodes, to determine a first set of resources associated with the first workload, to select a first one of the CXL devices to be used based upon the first set or resources, and to launch the first workload on the first processing node.

2. The information handling system of claim 1 , wherein the first CXL device includes a CXL memory device.

3. The information handling system of claim 2 , wherein the first set of resources includes a logical drive of the CXL memory device.

4. The information handling system of claim 3 , wherein, in launching the first workload on the first processing node, the workload orchestrator is further configured to direct the CXL switch to map the first processing node to the logical drive.

5. The information handling system of claim 4 , wherein the CXL switch includes a CXL fabric manager configured to partition the first CXL memory device to include the logical drive.

6. The information handling system of claim 1 , wherein the first CXL device includes a CXL accelerator device.

7. The information handling system of claim 6 , wherein the CXL accelerator device includes one of a graphics processing unit, a field programmable gate array, and an application specific integrated circuit.

8. The information handling system of claim 1 , wherein the workload orchestrator is further configured to receive a second workload to be instantiated on the first processing node, to determine that a second one of the processing nodes is underutilized, to determine a second set of resources associated with the second workload, to select a second one of the CXL devices to be used based upon the second set or resources, and to launch the second workload on the second processing node.

9. The information handling system of claim 1 , wherein the workload orchestrator is instantiated in the first processing node.

10. The information handling system of claim 1 , wherein the workload orchestrator is instantiated in the CXL switch.

11. A method, comprising:

coupling a plurality of processing nodes to a compute express link (CXL) switch;

coupling a plurality of CXL devices to the CXL switch;

receiving, by a workload orchestrator, a first workload to be instantiated on a first one of the processing nodes;

determining a first set of resources associated with the first workload;

selecting a first one of the CXL devices to be used based upon the first set or resources; and

launching the first workload on the first processing node.

12. The method of claim 11 , wherein the first CXL device includes a CXL memory device.

13. The method of claim 12 , wherein the first set of resources includes a logical drive of the CXL memory device.

14. The method of claim 13 , wherein, in launching the first workload on the first processing node, the method further comprise directing the CXL switch to map the first processing node to the logical drive.

15. The method of claim 14 , wherein:

the CXL switch includes a CXL fabric manager; and

the method further comprises partitioning, by the CXL fabric manager, the CXL memory device to include the logical drive.

16. The method of claim 11 , wherein the first CXL device includes a CXL accelerator device.

17. The method of claim 16 , wherein the CXL accelerator device includes one of a graphics processing unit, a field programmable gate array, and an application specific Integrated circuit.

18. The method of claim 11 , further comprising:

receiving, by the workload orchestrator, a second workload to be instantiated on the first processing node;

determining that a second one of the processing nodes is underutilized;

determining a second set of resources associated with the second workload;

selecting a second one of the CXL devices to be used based upon the second set or resources; and

launching the second workload on the second processing node.

19. The method of claim 11 , wherein the workload orchestrator is instantiated in one of the first processing node and the CXL switch.

20. An information handling system, comprising:

a plurality of processing nodes;

a compute express link (CXL) switch;

a plurality of CXL memory devices; and

a workload orchestrator configured to receive a workload to be instantiated on a particular one of the processing nodes, to determine a set of resources associated with the workload, to select a particular one of the CXL memory devices to be used based upon the set or resources, and to launch the workload on the processing node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2022
From: HAN, YUNFAN; WANG, ISAAC Q.; CHIN, JORDAN
To: DELL PRODUCTS L.P.
Reel/Frame 060486/0773 →
Continuity (1)
Related Publication 20240020174A1 · Jan 18, 2024
References Cited (2)
US 11144340B2 · Warnicke et al. · 2021 [cited by applicant]
US 20170192825A1 · Biberman et al. · 2017 [cited by applicant]