Gate driving circuit and display device including the same
A display device according to an aspect comprises a display panel that includes a plurality of pixels configured to display an image; a gate driving circuit configured to output respective scan signals to gate lines of the display panel; and a controller configured to (1) determine a deviation between the scan signals applied to the gate lines of the display panel and (2) compensate for the deviation when it is determined that the deviation is greater than a threshold.
1. A display device, comprising:
a display panel including a plurality of pixels configured to display an image;
a gate driving circuit configured to output respective scan signals to gate lines of the display panel; and
a controller configured to (1) determine a deviation between the scan signals applied to the gate lines of the display panel and (2) compensate for the deviation when it is determined that the deviation is greater than a threshold,
wherein the gate driving circuit includes a plurality of output buffers that are commonly connected to one Q node, each of the plurality of output buffers receives a corresponding one of a plurality of scan clock signals and output a scan signal to a corresponding gate line in response to a voltage of the Q node, and
wherein the controller determines the deviation between the scan signals output from the plurality of output buffers commonly connected to one Q node, and compensate for the deviation when it is determined that the deviation is greater than the threshold by controlling Q node voltage.
2. The display device of claim 1 , wherein the controller includes a sensor configured to determine the deviation between the scan signals applied to the gate lines of the display panel.
3. The display device of claim 2 , wherein the sensor is configured to determine the deviation between the scan signals by sensing a difference in charge amounts of the plurality of pixels disposed on the display panel.
4. The display device of claim 3 , wherein the sensor is configured to sense the difference in the charge amounts of the plurality of pixels by applying a sensing reference voltage to the plurality of pixels,
the sensing reference voltage is a voltage according to Equation 1 below:
V
data
′
=
a
REF
a
×
V
data
+
Φ
COMP
[
Equation
1
]
where V′ DATA is a compensation voltage as the sensing reference voltage, a REF /a is a gain compensation parameter, V DATA is a voltage before the compensation, and Φ COMP is an offset compensation parameter.
5. The display device of claim 2 , wherein the controller further includes a signal generator configured to determine the deviation between the scan signals applied to the gate lines of the display panel through the sensor and generate the Q node voltage control signal for controlling Q node voltage of output buffers of the gate driving circuit when the deviation is greater than the threshold.
6. The display device of claim 5 , wherein each of the plurality of output buffers includes a pull-up transistor commonly connected to the Q node and a pull-down transistor connected to the pull-up transistor.
7. The display device of claim 6 , wherein the Q node voltage is applied to a gate of the pull-up transistor of each of the plurality of output buffers.
8. The display device of claim 7 , wherein the Q node voltage control signal is a control signal configured to raise the Q node voltage applied to the gate of the pull-up transistor of each of the plurality of output buffers to a level.
9. The display device of claim 8 , wherein the controller further includes a signal output unit,
the display device further includes a power management integrated circuit configured to provide a voltage to the Q node;
the signal output unit is configured to provide the Q node voltage control signal generated by the signal generator to the power management integrated circuit.
10. A display device, comprising:
a display panel including a plurality of pixels configured to display an image;
a gate driving circuit configured to output respective scan signals to gate lines of the display panel; and
a controller configured to maintain a deviation between the scan signals to be less than a threshold,
wherein the gate driving circuit includes a plurality of output buffers that are commonly connected to one Q node, each of the plurality of output buffers receives a corresponding one of a plurality of scan clock signals and output a scan signal to a corresponding gate line in response to a voltage of the Q node, and
wherein the controller maintains the deviation between the scan signals output from the plurality of output buffers commonly connected to one Q node to be less than the threshold.
11. The display device of claim 10 , wherein the controller is configured to maintain the deviation between the scan signals to be less than the threshold by:
determining that a difference in charge amounts of the plurality of pixels is greater than a charge threshold, wherein the difference in the charge amounts is indicative of the deviation being greater than the threshold;
generating a control signal to reduce the deviation to be less than threshold.
12. The display device of claim 11 , wherein the controller is further configured to:
apply, based on the control signal, a voltage at a node of the gate driving circuit to maintain the deviation between the scan signals to be less than the threshold.
13. The display device of claim 12 , wherein the controller comprises:
a sensor;
a signal generator; and
a signal output unit.
14. The display device of claim 13 , wherein the sensor is configured to determine the difference in the charge amounts, and generate the control signal.
15. The display device of claim 13 , wherein the control signal is provided to a power management integrated circuit for increasing the voltage at the node, via the signal output unit.
16. The display device of claim 12 , wherein the node is a Q node of the gate driving circuit.
17. The display device of claim 12 , wherein the gate driving circuit includes a plurality of output buffers, and each of the plurality of output buffers includes a pull-up transistor and a pull-down transistor connected to the pull-up transistor.
18. The display device of claim 17 , wherein the voltage is applied to a gate of the pull-up transistor of each of the plurality of output buffers.
19. The display device of claim 11 , wherein the controller is configured to determine the difference in the charge amounts of the plurality of pixels by applying a sensing reference voltage to the plurality of pixels,
the sensing reference voltage is a voltage according to Equation 1 below:
V
data
′
=
a
REF
a
×
V
data
+
Φ
COMP
[
Equation
1
]
where V′ DATA is a compensation voltage as the sensing reference voltage, a REF /a is a gain compensation parameter, V DATA is a voltage before the compensation, and Φ COMP is an offset compensation parameter.