Semiconductor device including memory element
View Patent ↗Provided is a semiconductor device including a memory cell and a MOS transistor. The memory cell includes a first gate insulating layer and a first gate conductor layer surrounding a first pillar-shaped p layer erected on a first p layer substrate, and a second gate insulating layer, a second gate conductor layer, and N + layers surrounding a second pillar-shaped p layer connected to the first pillar-shaped p layer. The MOS transistor includes a third pillar-shaped p layer erected on a second p layer substrate connected to the first p layer substrate, and a third gate insulating layer, a third gate conductor layer, and N + layers surrounding a fourth pillar-shaped p layer placed on and in contact with the third pillar-shaped p layer. In a vertical direction, the second pillar-shaped p layer has a length shorter than a length of the fourth pillar-shaped p layer.
1. A semiconductor device comprising:
a memory element including
a first semiconductor pillar erected on a substrate in a vertical direction with respect to the substrate,
a first impurity region connected to a bottom of the first semiconductor pillar,
a first gate insulating layer placed in contact with a side surface of the first semiconductor pillar,
a first gate conductor layer placed in contact with the first gate insulating layer,
a second semiconductor pillar placed on and in contact with the first semiconductor pillar,
a first insulating layer placed on the first gate conductor layer and surrounding a vicinity of a boundary between the first semiconductor pillar and the second semiconductor pillar,
a second impurity region and a third impurity region placed in contact with the second semiconductor pillar and on the first insulating layer and opposed to each other in a horizontal direction,
a second gate insulating layer placed in contact with at least one of an upper surface and opposite side surfaces of the second semiconductor pillar between the second impurity region and the third impurity region in the horizontal direction, and
a second gate conductor layer placed in contact with the second gate insulating layer; and
a MOS transistor including
a third semiconductor pillar erected on the substrate in the vertical direction with respect to the substrate,
a first material layer surrounding the third semiconductor pillar and containing an insulating material or a conductor material insulated from the third semiconductor pillar,
a fourth semiconductor pillar placed on and in contact with the third semiconductor pillar,
a third gate insulating layer placed in contact at least with opposite side surfaces of the fourth semiconductor pillar,
a third gate conductor layer placed in contact with the third gate insulating layer, and
a fourth impurity region and a fifth impurity region placed in contact with a portion of the fourth semiconductor pillar and opposed to each other in the horizontal direction, the portion being not covered by the third gate insulating layer, wherein
in the vertical direction, the second semiconductor pillar has a length shorter than a length of the fourth semiconductor pillar.
2. The semiconductor device according to claim 1 , wherein in the vertical direction, the first semiconductor pillar and the third semiconductor pillar have upper surfaces at a substantially same position.
3. The semiconductor device according to claim 1 , wherein in the vertical direction, the first semiconductor pillar and the third semiconductor pillar have bottoms at a substantially same position.
4. The semiconductor device according to claim 1 , wherein
the first material layer includes
a second insulating layer surrounding the third semiconductor pillar, and
a first conductor layer surrounding the second insulating layer, and
a temporally-constant or varying voltage is applied to the first conductor layer.
5. The semiconductor device according to claim 4 , wherein the MOS transistor includes a sixth impurity region connected to a bottom of the third semiconductor pillar.
6. The semiconductor device according to claim 1 , wherein the MOS transistor is a Fin MOS transistor composed of the fourth semiconductor pillar, the third gate insulating layer, the third gate conductor layer, the fourth impurity region, and the fifth impurity region.
7. The semiconductor device according to claim 1 , wherein in the memory element, a transistor composed of the second semiconductor pillar, the second gate insulating layer, the second gate conductor layer, the second impurity region, and the third impurity region is a planar MOS transistor.
8. The semiconductor device according to claim 1 , wherein in the memory element, a transistor composed of the second semiconductor pillar, the second gate insulating layer, the second gate conductor layer, the second impurity region, and the third impurity region is a Fin MOS transistor.
9. The semiconductor device according to claim 1 , wherein
in the memory element, a transistor composed of the second semiconductor pillar, the second gate insulating layer, the second gate conductor layer, the second impurity region, and the third impurity region is a planar MOS transistor having a U-shaped channel,
the second semiconductor pillar has a vertical cross-section having a U-shape, and
a length in the vertical direction of the second semiconductor pillar at a bottom of the U-shape is shorter than the length of the fourth semiconductor pillar.
10. The semiconductor device according to claim 1 , wherein the first impurity region is connected to a bottom of a semiconductor pillar of another memory cell adjacent to the first semiconductor pillar.
11. The semiconductor device according to claim 1 , wherein the first impurity region is isolated from an impurity layer at a bottom of a semiconductor pillar of another memory cell adjacent to the first semiconductor pillar.
12. The semiconductor device according to claim 1 , wherein the first gate conductor layer is divided into two or more layers in the vertical direction.
13. The semiconductor device according to claim 1 , wherein the first gate conductor layer is divided into two or more layers in a horizontal cross-section.
14. The semiconductor device according to claim 1 , wherein the semiconductor device performs
a memory write operation of controlling voltages to be applied to the second impurity region, the third impurity region, and the second gate conductor layer to generate, in the second semiconductor pillar, a group of electrons and a group of holes by an impact ionization phenomenon based on a current caused to flow between the second impurity region and the third impurity region or by a gate-induced drain leakage current, and causing part or whole of the group of electrons or the group of holes which are majority carriers in the group of electrons and the group of holes as generated to remain mainly in the first semiconductor pillar, and
a memory erase operation of extracting the group of electrons or the group of holes which remain and are majority carriers from any or all of the first impurity region, the second impurity region, and the third impurity layer.
15. The semiconductor device according to claim 1 , wherein the semiconductor device performs
a memory write operation of controlling voltages to be applied to one or both of the second impurity region and the third impurity region, the first impurity region, and the first gate conductor layer to generate, in the first semiconductor pillar, a group of electrons and a group of holes by an impact ionization phenomenon based on a current caused to flow between one or both of the second impurity region and the third impurity region, and the first impurity region or by a gate-induced drain leakage current, and causing part or whole of the group of electrons or the group of holes which are majority carriers in the group of electrons and the group of holes as generated to remain mainly in the first semiconductor pillar, and
a memory erase operation of extracting the group of electrons or the group of holes which remain and are majority carriers from any or all of the first impurity region, the second impurity region, and the third impurity layer.