Method and apparatus for reducing audible buzz from a switching-mode power supply
View Patent ↗An apparatus of the subject technology includes a circuit to switch a first current based on a switching frequency and generate an output voltage, and a first circuit coupled to the circuit to adjust the switching frequency through changing a frequency of the circuit to a value higher than a threshold.
1. An apparatus, comprising:
a regulator circuit configured to switch a first current based on a switching frequency and generate an output voltage; and
a first circuit coupled to a boost converter and configured to adjust the switching frequency by changing a pulse-frequency-modulation (PFM) frequency of a clock pulse of the regulator circuit to a value higher than a threshold;
a second circuit configured to generate a second current based on a digital code, wherein the digital code is generated based on a logic value, wherein the second current is used as an input to the boost converter to regulate an output voltage of the boost converter;
wherein the second circuit comprises a calculator circuit configured to generate the logic value based on an output of a comparator, an input of the comparator coupled to an output of the comparator, an input of the comparator coupled to an output of the boost converter; and
an accumulator circuit coupled to the comparator and configured to generate the digital code based on the logic value.
2. The apparatus of claim 1 , further comprising the second circuit configured to generate a second current to control the output voltage of the regulator circuit.
3. The apparatus of claim 2 , wherein the second circuit comprises a digital-to-analog converter (DAC) configured to generate the second current based on the digital code.
4. The apparatus of claim 3 , wherein the second circuit further comprises an accumulator circuit configured to generate the digital code based on the logic value.
5. The apparatus of claim 1 , wherein the second circuit further comprises the comparator configured to:
compare the output voltage with a reference voltage, and
generate the output of the comparator based on the comparison.
6. The apparatus of claim 1 , wherein the first current comprises a pulsed output current of the circuit.
7. The apparatus of claim 1 , wherein the first circuit further comprises a control circuit configured to change the PFM frequency by skipping a plurality of switching pulses.
8. The apparatus of claim 7 , wherein the control circuit is configured to determine a count N of the plurality of switching pulses based on the pulse-width modulation (PWM) frequency of the regulator circuit and the threshold.
9. The apparatus of claim 8 , wherein the control circuit is configured to cause periodic skipping of N switching pulses per each N+1 switching pulses of the plurality of switching pulses.
10. The apparatus of claim 8 , wherein the control circuit is configured to adjust the switching frequency in a time less than a millisecond.
11. An apparatus, comprising:
a regulator circuit configured to provide a pulsed output current and comprising:
a first circuit coupled to the regulator circuit and configured to maintain a switching frequency of the pulsed output current above a threshold frequency by changing a pulse-frequency-modulation (PFM) frequency of a clock pulse of the regulator circuit by skipping a plurality of switching pulses;
a second circuit configured to generate a second current, based on a digital code generated by an accumulator circuit to regulate an output voltage of the regulator circuit; and
wherein the accumulator circuit is configured to generate the digital code based on a logic value that is generated based on a comparison between the output voltage of the regulator circuit and a reference voltage.
12. The apparatus of claim 11 , wherein the first circuit includes a control circuit configured to determine a count N of the plurality of switching pulses based on the pulse-width modulation (PWM) frequency of the regulator circuit and the threshold frequency.
13. The apparatus of claim 12 , wherein the control circuit is configured to cause periodic skipping of N switching pulses per each N+1 switching pulses of the plurality of switching pulses.
14. The apparatus of claim 11 , wherein the regulator circuit further comprises the second circuit configured to generate a second current to regulate an output voltage of the regulator circuit.
15. The apparatus of claim 14 , wherein the second circuit comprises a digital-to-analog converter (DAC) configured to generate the second current based on the digital code generated by the accumulator circuit.
16. A communication device, comprising:
a boost converter coupled to a first circuit and a second circuit, wherein:
the first circuit is configured to determine a count of a plurality of switching pulses based on a pulse-frequency-modulation (PFM) frequency of a clock pulse of the boost converter and change the PFM frequency via selectively skipping switching pulses, based at least on the count, to adjust a switching frequency of the boost converter, and
the second circuit is configured to generate a second current to regulate an output voltage of the boost converter; and
wherein the second circuit is configured to generate the second current based on a digital code and wherein the digital code is generated based on a logic value that is generated based on a comparison between the output voltage of the boost converter and a reference voltage.
17. The communication device of claim 16 , wherein the first circuit comprises a control circuit configured to:
determine a count N of a plurality of switching pulses based on the pulse-width modulation (PWM) frequency of the boost converter and an audio-frequency threshold, and
cause selective skipping of the switching pulses by selectively skipping N switching pulses per each N+1 switching pulses of the plurality of switching pulses.
18. The communication device of claim 16 , wherein the second circuit comprises a digital-to-analog converter (DAC) configured to generate the second current based on the digital code generated by an accumulator circuit, and wherein the accumulator circuit is configured to generate the digital code based on the logic value that is generated based on the comparison between the output voltage of the boost converter and the reference voltage.