Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.
1. A semiconductor device, comprising:
a stack structure including first electrodes and insulating layers alternately stacked on each other;
a second electrode passing through the stack structure; and
variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes,
wherein the first electrodes include first sidewalls that each face the second electrode,
wherein the insulating layers include second sidewalls that each face the second electrode,
wherein at least a part of each of the variable resistance patterns protrudes farther towards the second electrode than a corresponding one of the second sidewalls, and
wherein the second electrode includes an air gap overlapping at least one of the variable resistance patterns.
2. The semiconductor device of claim 1 , wherein each of the variable resistance patterns includes a first portion interposed between an adjacent pair of the insulating layers and a second portion extending into the second electrode.
3. The semiconductor device of claim 2 , wherein the variable resistance patterns include a first variable resistance pattern located at an upper portion of the stack structure and a second variable resistance pattern located at a lower portion of the stack structure, and
wherein the second portion of the first variable resistance pattern protrudes farther towards the second electrode than that of the second variable resistance pattern.
4. The semiconductor device of claim 2 , wherein the first sidewall of the corresponding one of the first electrodes is spaced farther apart from a sidewall of the second electrode than the corresponding one of the second sidewalls.
5. The semiconductor device of claim 1 , wherein each of the variable resistance patterns includes a first portion interposed between the corresponding one of the first electrodes and the second electrode and a second portion interposed between a corresponding one of the insulating layers and the second electrode, and
wherein the first portion and the second portion extend into the second electrode.
6. The semiconductor device of claim 5 , wherein the first sidewall of the corresponding one of the first electrodes is aligned with the corresponding one of the second sidewalls.
7. The semiconductor device of claim 1 , wherein the variable resistance patterns are spaced apart from each other in a direction in which the first electrodes and the insulating layers are stacked.
8. The semiconductor device of claim 1 , wherein each of the variable resistance patterns includes a third sidewall contacting the first sidewall of the corresponding one of the first electrodes and a fourth sidewall contacting the second electrode, and
wherein the fourth sidewall includes a curved surface.
9. The semiconductor device of claim 1 , wherein the second electrode comprises:
a first portion extending in a direction in which the first electrodes and the insulating layers are stacked; and
second portions protruding from the first portion, each of the second portions being disposed between an adjacent pair of the variable resistance patterns.
10. The semiconductor device of claim 9 , wherein each of the second portions contact a corresponding one of the insulating layers.
11. The semiconductor device of claim 9 , wherein the air gap is included in at least one of the second portions.
12. The semiconductor device of claim 1 , wherein each of the variable resistance patterns includes a chalcogenide that maintains an amorphous state when a program operation is performed.
13. The semiconductor device of claim 1 , further comprising:
at least one of switching patterns and third electrodes between the first electrodes and the variable resistance patterns.
14. The semiconductor device of claim 1 , wherein the air gap is disposed between a neighboring pair of the variable resistance patterns in a specific direction, the first electrodes and the insulating layers being stacked in the specific direction.
15. A semiconductor device, comprising:
a stack structure including first electrodes and insulating layers alternately stacked on each other,
a second electrode passing through the stack structure; and
variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes,
wherein the first electrodes include first sidewalls that each face the second electrode,
wherein the insulating layers include second sidewalls that each face the second electrode, and
wherein each of the variable resistance patterns contacts a corresponding one of the first sidewalls and a corresponding one of the second sidewalls, and
wherein the second electrode includes an air gap overlapping at least one of the variable resistance patterns.
16. The semiconductor device of claim 15 , wherein each of the variable resistance patterns covers a corner of a corresponding one of the insulating layers and extends along the corresponding one of the second sidewalls.
17. The semiconductor device of claim 15 , wherein the variable resistance patterns are spaced apart from each other.
18. The semiconductor device of claim 15 , wherein the second electrode protrudes between at least one adjacent pair of the variable resistance patterns.
19. The semiconductor device of claim 15 , further comprising:
at least one of switching patterns and third electrodes between the first electrodes and the variable resistance patterns.
20. The semiconductor device of claim 15 , wherein the air gap is disposed between a neighboring pair of the variable resistance patterns in a specific direction, the first electrodes and the insulating layers being stacked in the specific direction.