Three-dimensional semiconductor device and method of fabricating the same
A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.
1. A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region comprising a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
a second active region on the first active region, the second active region comprising an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern;
a gate electrode on the lower channel pattern and the upper channel pattern;
a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction;
a first active contact coupled to the lower contact; and
a second active contact coupled to the upper source/drain pattern,
wherein a first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.
2. The three-dimensional semiconductor device of claim 1 , wherein a ratio of the second width to the first width ranges from 0.1 to 0.5.
3. The three-dimensional semiconductor device of claim 1 , wherein the lower contact is offset from a center of the lower source/drain pattern in the second direction.
4. The three-dimensional semiconductor device of claim 1 , wherein each of the lower channel pattern and the upper channel pattern comprises a plurality of semiconductor patterns, which are vertically spaced apart from each other, and
wherein the gate electrode encloses each of the plurality of semiconductor patterns.
5. The three-dimensional semiconductor device of claim 1 , further comprising a dummy channel pattern interposed between the lower channel pattern and the upper channel pattern,
wherein the dummy channel pattern is spaced apart from the lower source/drain pattern and the upper source/drain pattern.
6. The three-dimensional semiconductor device of claim 1 , wherein the upper source/drain pattern comprises a first sub-pattern and a second sub-pattern spaced apart from the first sub-pattern in the second direction, and
wherein the second active contact comprises a first contact and a second contact, which are respectively coupled to the first sub-pattern and the second sub-pattern.
7. The three-dimensional semiconductor device of claim 6 , wherein the second active contact further comprises a connecting portion connecting the first contact to the second contact.
8. The three-dimensional semiconductor device of claim 6 , wherein the lower contact is vertically offset from each of the first sub-pattern and the second sub-pattern.
9. The three-dimensional semiconductor device of claim 1 , further comprising interconnection lines on, and electrically connected to, the first active contact and the second active contact.
10. The three-dimensional semiconductor device of claim 1 , wherein the first active region and the second active region are provided in an extra gate (EG) device region.
11. A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region comprising a pair of lower channel patterns and a lower source/drain pattern between the pair of lower channel patterns;
a second active region on the first active region, the second active region comprising a pair of upper channel patterns and an upper source/drain pattern between the pair of upper channel patterns;
gate electrodes provided on the pair of lower channel patterns and the pair of upper channel patterns;
a lower contact electrically connected to the lower source/drain pattern;
a first active contact coupled to the lower contact; and
a second active contact coupled to the upper source/drain pattern,
wherein the upper source/drain pattern comprises a first sub-pattern connected to one of the pair of upper channel patterns, and a second sub-pattern connected to another one of the pair of upper channel patterns,
wherein the first sub-pattern is separated from the second sub-pattern, and
wherein the second active contact comprises a first contact and a second contact, which are respectively coupled to the first sub-pattern and the second sub-pattern.
12. The three-dimensional semiconductor device of claim 11 , wherein the second active contact further comprises a connecting portion connecting the first contact to the second contact.
13. The three-dimensional semiconductor device of claim 11 , further comprising an interconnection line on the second active contact,
wherein the interconnection line is provided to electrically connect the first contact to the second contact.
14. The three-dimensional semiconductor device of claim 11 , wherein the lower contact has a bar shape extending from the lower source/drain pattern in a first direction, and
wherein the first sub-pattern is spaced apart from the second sub-pattern in a second direction crossing the first direction.
15. The three-dimensional semiconductor device of claim 11 , wherein the first contact is extended from a top surface of the first sub-pattern along a side surface of the first sub-pattern, and
wherein the second contact is extended from a top surface of the second sub-pattern along a side surface of the second sub-pattern.
16. A three-dimensional semiconductor device, comprising:
a first active region on a first region of a substrate, the first active region comprising a first lower channel pattern and a first lower source/drain pattern connected to the first lower channel pattern;
a second active region on the first active region, the second active region comprising a first upper channel pattern and a first upper source/drain pattern connected to the first upper channel pattern;
a gate electrode on the first lower channel pattern and the first upper channel pattern;
a first peripheral active region on a second region of the substrate, the first peripheral active region comprising a second lower channel pattern and a second lower source/drain pattern connected to the second lower channel pattern;
a second peripheral active region on the first peripheral active region, the second peripheral active region comprising a second upper channel pattern and a second upper source/drain pattern connected to the second upper channel pattern;
a peripheral gate electrode on the second lower channel pattern and the second upper channel pattern;
a first active contact coupled to the first upper source/drain pattern; and
a second active contact coupled to the second upper source/drain pattern,
wherein the first upper channel pattern comprises a pair of first upper channel patterns, which are adjacent to each other,
wherein the first upper source/drain pattern is provided as a continuous body connecting the pair of first upper channel patterns to each other,
wherein the second upper channel pattern comprises a pair of second upper channel patterns, which are adjacent to each other,
wherein the second upper source/drain pattern comprises a first sub-pattern connected to one of the pair of second upper channel patterns, and a second sub-pattern connected to another one of the pair of second upper channel patterns, and
wherein the first sub-pattern is separated from the second sub-pattern.
17. The three-dimensional semiconductor device of claim 16 , wherein the second active contact comprises a first contact and a second contact, which are respectively coupled to the first sub-pattern and the second sub-pattern.
18. The three-dimensional semiconductor device of claim 17 , wherein the second active contact further comprises a connecting portion connecting the first contact to the second contact.
19. The three-dimensional semiconductor device of claim 16 , wherein the first region comprises a single gate (SG) device, and
wherein the second region comprises an extra gate (EG) device.
20. The three-dimensional semiconductor device of claim 16 , further comprising:
a first lower contact electrically connected to the first lower source/drain pattern; and
a second lower contact electrically connected to the second lower source/drain pattern,
wherein a ratio of a width of the first lower contact to a width of the first lower source/drain pattern is greater than a ratio of a width of the second lower contact to a width of the second lower source/drain pattern.