Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a first oxide semiconductor layer between a first conductive layer and a second conductive layer; a first gate electrode; a first electrode; a second electrode; a first capacitor insulating film between the first electrode and the second electrode including a first region and a second region between the first region and the second electrode, concentration of the Ti is higher in the second region than the first region; a third conductive layer; a second oxide semiconductor layer between the third conductive layer and a fourth conductive layer; a second gate electrode; a third electrode; a fourth electrode; and a second capacitor insulating film between the third electrode and the fourth electrode, and including a third region and a fourth region between the third region and the fourth electrode, concentration of Ti is higher in the fourth region than the third region.
1. A semiconductor memory device comprising:
a first conductive layer;
a second conductive layer;
a first oxide semiconductor layer provided between the first conductive layer and the second conductive layer;
a first gate electrode surrounding the first oxide semiconductor layer;
a first gate insulating film provided between the first oxide semiconductor layer and the first gate electrode;
a first electrode provided in a first direction with respect to the second conductive layer, the first direction being a direction connecting the first conductive layer and the second conductive layer, the second conductive layer provided between the first oxide semiconductor layer and the first electrode, the first electrode electrically connected to the second conductive layer, and the first electrode containing titanium (Ti);
a second electrode surrounding the first electrode and containing the titanium (Ti);
a first capacitor insulating film provided between the first electrode and the second electrode, the first capacitor insulating film including a first region and a second region between the first region and the second electrode, an atomic concentration of the titanium (Ti) of the second region being higher than an atomic concentration of the titanium (Ti) of the first region;
a third conductive layer provided in the first direction with respect to the first conductive layer, the third conductive layer electrically connected to the first conductive layer;
a fourth conductive layer provided in the first direction with respect to the third conductive layer, the third conductive layer provided between the first conductive layer and the fourth conductive layer;
a second oxide semiconductor layer provided between the third conductive layer and the fourth conductive layer;
a second gate electrode surrounding the second oxide semiconductor layer;
a second gate insulating film provided between the second oxide semiconductor layer and the second gate electrode;
a third electrode provided in the first direction with respect to the fourth conductive layer, the fourth conductive layer provided between the second oxide semiconductor layer and the third electrode, the third electrode electrically connected to the fourth conductive layer, and the third electrode containing the titanium (Ti);
a fourth electrode surrounding the third electrode and containing the titanium (Ti); and
a second capacitor insulating film provided between the third electrode and the fourth electrode, the second capacitor insulating film including a third region and a fourth region between the third region and the fourth electrode, an atomic concentration of the titanium (Ti) of the fourth region being higher than an atomic concentration of the titanium (Ti) of the third region.
2. The semiconductor memory device according to claim 1 , wherein the atomic concentration of the titanium (Ti) of the second region is equal to or more than ten times the atomic concentration of the titanium (Ti) of the first region, and
the atomic concentration of the titanium (Ti) of the fourth region is equal to or more than ten times the atomic concentration of the titanium (Ti) of the third region.
3. The semiconductor memory device according to claim 1 , wherein the atomic concentration of the titanium (Ti) of the second region is equal to or more than 1×10 17 cm −3 , and the atomic concentration of the titanium (Ti) of the fourth region is equal to or more than 1×10 17 cm −3 .
4. The semiconductor memory device according to claim 1 , further comprising an insulating layer provided between the third electrode and the fourth electrode in the first direction, the insulating layer being in contact with the third electrode and the fourth electrode, and a material of the insulating layer being different from a material of the second capacitor insulating film.
5. The semiconductor memory device according to claim 1 , further comprising a substrate, wherein the first capacitor insulating film is provided between the substrate and the second capacitor insulating film.
6. The semiconductor memory device according to claim 1 , wherein the first electrode, the second electrode, the third electrode, and the fourth electrode contain nitrogen (N).
7. The semiconductor memory device according to claim 1 , wherein the first capacitor insulating film and the second capacitor insulating film contain oxygen (O).
8. The semiconductor memory device according to claim 1 , wherein the first capacitor insulating film and the second capacitor insulating film contain at least one metal element selected from a group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), yttrium (Y), lanthanum (La), and tantalum (Ta).
9. The semiconductor memory device according to claim 1 , further comprising a wiring layer extending in a second direction intersecting the first direction, the wiring layer electrically connected to the first conductive layer and the third conductive layer,
wherein the first gate electrode and the second gate electrode extend in a third direction intersecting the first direction and the second direction.
10. The semiconductor memory device according to claim 1 , wherein the first oxide semiconductor layer and the second oxide semiconductor layer contain indium (In) and zinc (Zn).