Integrated circuit including standard cell and method of designing the same
An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.
1. An integrated circuit comprising a plurality of standard cells performing a same function,
wherein the plurality of standard cells include a first standard cell and a second standard cell, and
the first standard cell and the second standard cell are the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.
2. The integrated circuit of claim 1 , wherein the first standard cell and the second standard cell are different from each other in terms of a position of a gate contact formed over the gate line.
3. The integrated circuit of claim 1 , wherein the first standard cell and the second standard cell are the same as each other in terms of a position of a gate contact formed over the gate line.
4. The integrated circuit of claim 1 , wherein an output pin of the first standard cell that outputs an output signal to the outside of the first standard cell is formed as a pattern of a first metal layer formed over the gate line.
5. The integrated circuit of claim 1 , wherein an output pin of the first standard cell that outputs an output signal to the outside of the first standard cell is formed as an active contact contacting a source/drain region formed in an active region of the first standard cell.
6. The integrated circuit of claim 5 , wherein the first standard cell and the second standard cell are different from each other in terms of a position of a via that is arranged to output the output signal and that is formed over the active contact.
7. The integrated circuit of claim 1 , wherein the first standard cell includes a plurality of gate lines through which the input signal is input.
8. An integrated circuit comprising:
a plurality of standard cells;
a first metal layer and a second metal layer formed over the first metal layer, the first metal layer and the second metal layer being for interconnecting the plurality of standard cells,
wherein patterns of the first metal layer extend in a first horizontal direction,
patterns of the second metal layer extend in a second horizontal direction, and
at least one standard cell among the plurality of standard cells includes a gate line, which extends in the second horizontal direction and through which an input signal is received, as an input pin.
9. The integrated circuit of claim 8 , wherein the at least one standard cell includes a plurality of gate lines through which the input signal is input, as an input pin, and
the first metal layer includes a routing line that is over the plurality of gate lines and that electrically connects the plurality of gate lines to each other.
10. The integrated circuit of claim 8 , wherein, in the at least one standard cell, a no-routing region is defined in which formation of a gate via connecting the gate line and the first metal layer to each other therebetween is prohibited.
11. The integrated circuit of claim 8 , wherein the at least one standard cell includes an output pin that is arranged to output an output signal to the outside of the at least one standard cell and that is formed as a pattern of the first metal layer.
12. The integrated circuit of claim 8 , wherein the at least one standard cell includes:
an active region extending in the first horizontal direction; and
an output pin that is arranged to output an output signal to the outside and that is formed as an active contact contacting a source/drain region formed in the active region.
13. The integrated circuit of claim 8 , wherein the at least one standard cell includes an active region extending in the first horizontal direction, and
a nanosheet that is formed to be surrounded by the gate line is formed in the active region.
14. An integrated circuit comprising:
a plurality of standard cells; and
a first metal layer and a second metal layer formed over the first metal layer, the first metal layer and the second metal layer being for interconnecting the plurality of standard cells,
wherein patterns of the first metal layer extend in a first horizontal direction,
patterns of the second metal layer extend in a second horizontal direction, and
a first standard cell among the plurality of standard cells includes a first gate contact, which contacts a first gate line, which extends in the second horizontal direction and through which an input signal is received, as an input pin.
15. The integrated circuit of claim 14 , wherein the first standard cell further includes a second gate line, and a second gate contact that contacts the second gate line and that is formed as an input pin, and
the first metal layer includes a routing line electrically connecting the first gate contact and the second gate contact to each other.
16. The integrated circuit of claim 14 , wherein the first standard cell further includes a third gate contact contacting the first gate line, and
the third gate contact includes a dummy contact electrically isolated from the patterns of the first metal layer.
17. The integrated circuit of claim 14 , wherein the first standard cell further includes a fourth gate contact contacting the first gate line, and
in the first standard cell, a no-routing region is defined in which formation of a gate via connecting the fourth gate contact and the first metal layer to each other therebetween is prohibited.
18. The integrated circuit of claim 14 , wherein the first standard cell includes an output pin that is arranged to output an output signal to the outside of the first standard cell and that is formed as a pattern of the first metal layer.
19. The integrated circuit of claim 14 , wherein the first standard cell includes:
an active region extending in the first horizontal direction; and
an output pin that is arranged to output an output signal to the outside of the first standard cell and that is formed as an active contact contacting a source/drain region formed in the active region.
20. The integrated circuit of claim 14 , wherein the plurality of standard cells include a second standard cell performing a same function as the first standard cell,
the second standard cell includes a gate line through which an input signal is received and which extends in the second horizontal direction, and a gate contact contacting the gate line, and
the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns other than the first gate contact of the first standard cell and the gate contact of the second standard cell.