IP Library › Granted Patent US 12,440,968
Granted Patent B2
US 12,440,968 · App. 17/776,419 · Granted Oct 14, 2025

Control and monitoring of a machine arrangement

Inventor: Yevgen Kogan (Augsburg, DE)
Assignee: KUKA Deutschland GmbH
B25J9/161B25J9/1674G05B2219/2205G05B2219/33332G05B2219/34482G06F11/3055
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,440,968
App. No.
17/776,419
Granted
Oct 14, 2025
Kind
B2
Abstract

A method for controlling and/or monitoring a machine arrangement having at least one machine, in particular at least one robot, with the aid of a processor arrangement having a plurality of processors each with at least one core. The method includes selecting, in particular temporarily selecting, a first available and at least one further available core on the proviso that these cores are implemented, in particular arranged, on different processors of the processor arrangement, in particular during operation of the machine arrangement and/or on the basis of an updated directory and/or on the basis, in particular as a result, of an ascertained need for redundant processing of process signals; processing process signals redundantly with the aid of these selected cores; and controlling and/or monitoring the machine arrangement on the basis of this processing.

Claims (85)

1. A system for controlling and/or monitoring a machine arrangement that includes at least one machine with the aid of a processor arrangement having a plurality of processors, each with at least one core, the system comprising:

means for classifying at least one core as available or unavailable on the basis of a utilization level of the at least one core specified in a directory;

means for selecting a first available core and at least one second available core on the proviso that the first and second cores are implemented on different processors of the processor arrangement;

means for processing first process signals redundantly with the aid of the selected first and second cores;

means for controlling and/or monitoring the machine arrangement on the basis of the first process signals;

(d) means for selecting a third available core different from the first core and at least one fourth available core different from the first core, on the proviso that the third available core and the at least one fourth available core are implemented on different processors of the processor arrangement;

(e) means for processing second process signals redundantly with the aid of the third and fourth selected cores; and

(f) means for controlling and/or monitoring the machine arrangement on the basis of the second process signals;

wherein selecting is carried out on the basis of an updated directory.

2. The system of claim 1 , wherein at least one of:

the at least one machine is at least one robot;

selecting the first and second cores comprises temporarily selecting the first and second cores;

the first and second cores are arranged on different processors; or

selecting is carried out at least one of:

during operation of the machine arrangement,

on the basis of an updated directory,

on the basis of an ascertained need for redundant processing of process signals, or

as a result of an ascertained need for redundant processing of process signals.

3. A method for controlling and/or monitoring a machine arrangement comprising at least one machine with the aid of a processor arrangement having a plurality of processors each with at least one core, the method comprising:

classifying at least one core as available or unavailable on the basis of a utilization level of the at least one core specified in a directory;

(a) selecting a first available core and at least one second available core on the proviso that the first and second cores are implemented on different processors of the processor arrangement;

(b) processing first process signals redundantly with the aid of the selected first and second cores;

(c) controlling and/or monitoring the machine arrangement on the basis of the first process signals;

(d) selecting a third available core different from the first core and at least one fourth available core different from the first core, on the proviso that the third available core and the at least one fourth available core are implemented on different processors of the processor arrangement;

(e) processing second process signals redundantly with the aid of the third and fourth selected cores; and

(f) controlling and/or monitoring the machine arrangement on the basis of the second process signals;

wherein selecting is carried out on the basis of an updated directory.

4. The method of claim 3 , wherein at least one of:

selecting the third and fourth cores comprises temporarily selecting the third and fourth cores;

the third and fourth cores are arranged on different processors;

selecting is carried out at least one of:

during or after completion of step (c),

on the basis of an ascertained need for redundant processing of process signals, or

as a result of an ascertained need for redundant processing of process signals; or

controlling and/or monitoring the machine arrangement on the basis of the second process signals comprises controlling and/or monitoring the same machine controlled and/or monitored on the basis of the first process signals.

5. The method of claim 3 , further comprising at least one of the following steps:

(I) classifying at least one of:

at least one core that is currently unselected as available,

at least one of the cores selected in step (a) after the completion of step (c), or

at least one of the cores selected in step (d) upon completion of step (f); or

(II) classifying at least one currently selected core as unavailable.

6. The method of claim 5 , wherein at least one of:

cores are classified as available or unavailable in a directory;

classifying at least one core comprises marking the at least one core; or

classifying at least one core comprises classifying the at least one core in a directory.

7. The method of claim 3 , further comprising repeating steps (a) to (c).

8. The method of claim 3 , further comprising repeating at least one of:

steps (a) to (c); or

steps (d) to (e).

9. The method of claim 5 , wherein at least one of:

steps a) to (c) are repeated;

steps (d) to (e) are repeated; or

at least one of steps (I), or (II) are repeated.

10. The method of claim 3 , wherein selecting cores in at least one of steps (a) or (d) comprises selecting the cores on the basis of a spatial position of the respective processors.

11. The method of claim 3 , wherein at least one of:

(I) in step (a), at least one of:

a core of a processor of a machine controller of a machine of the machine arrangement that is controlled or monitored in step (c),

a core of a processor of a controller of a machine of the machine arrangement arranged in the same cell as the controlled or monitored machine, or

a core of a processor located in close proximity to this controlled or monitored machine and/or machine controller compared to a core of a processor located further away,

is/are prioritized relative to at least one other core;

(II) in step (d), at least one of:

a core of a processor of a machine controller of a machine of the machine arrangement that is controlled or monitored in step (f),

a core of a processor of a controller of a machine of the machine arrangement arranged in the same cell as the controlled or monitored machine, or

a core of a processor located in close proximity to this controlled or monitored machine and/or machine controller compared to a core of a processor located further away,

is/are prioritized relative to at least one other core; or

(III) in at least one of step (a) or step (d), selecting cores comprises selecting on the basis of the respective processor architecture.

12. The method of claim 11 , wherein selecting cores on the basis of the respective processor architecture comprises selecting cores in a prioritized manner on processors with different architectures.

13. The method of claim 3 , further comprising communicating, via at least one shared data connection, between at least one of:

at least one selected core with at least one other selected core;

at least one selected core with at least one process signal source, or

at least one selected core with at least one controller of the machine arrangement.

14. The method of claim 3 , wherein at least one of:

cores selected in step (a) are implemented on different processors of the same computer, or the first core selected in step (a) is implemented on a processor of a computer and the at least one second core selected in step (a) is implemented on a processor of a different computer; or

cores selected in step (d) are implemented on different processors of the same computer, or the third core selected in step (d) is implemented on a processor of a computer and the at least one fourth core selected in step (d) is implemented on a processor of a different computer.

15. The method of claim 14 , wherein:

cores implemented on different processors are arranged on different processors.

16. The method of claim 3 , wherein at least one of:

the at least one machine is at least one robot;

selecting the first and second cores comprises temporarily selecting the first and second cores;

the first and second cores are arranged on different processors; or

selecting is carried out at least one of:

during operation of the machine arrangement,

on the basis of an ascertained need for redundant processing of process signals, or

as a result of an ascertained need for redundant processing of process signals.

17. A computer program code stored on a non-transitory, computer-readable medium, the program code, when executed on a computer, causing the computer to carry out a method according to claim 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2022
From: KOGAN, YEVGEN
To: KUKA DEUTSCHLAND GMBH
Reel/Frame 059927/0297 →
Priority Claims (1)
DE 10 2019 217 427.2 · Nov 12, 2019 · national
Continuity (1)
Related Publication 20220402121A1 · Dec 22, 2022
References Cited (36)
US 7383423B1 · Hughes · 2008 [cited by examiner]
US 8037350B1 · Aggarwal et al. · 2011 [cited by applicant]
US 9891978B1 · Fejfar · 2018 [cited by examiner]
US 10423158B1 · Hadlich · 2019 [cited by examiner]
US 20060212677A1 · Fossum · 2006 [cited by examiner]
US 20120036398A1 · Moyer et al. · 2012 [cited by applicant]
US 20160216704A1 · Koh · 2016 [cited by examiner]
US 20180329397A1 · Izzo · 2018 [cited by examiner]
US 20190056719A1 · Ong et al. · 2019 [cited by applicant]
US 20190155681A1 · Lee et al. · 2019 [cited by applicant]
US 20200073370A1 · Izzo et al. · 2020 [cited by applicant]
US 20200150635A1 · Grosch et al. · 2020 [cited by applicant]
US 20230156531A1 · Miklós · 2023 [cited by examiner]
CN 108023809A · 2018 [cited by applicant]
CN 114930258A · 2022 [cited by examiner]
DE 102018207399A1 · 2018 [cited by applicant]
DE 102018120345A1 · 2019 [cited by applicant]
DE 102019217427A1 · 2021 [cited by examiner]
EP 3316052A1 · 2018 [cited by applicant]
EP 3654121A1 · 2020 [cited by applicant]
JP 2008015638A · 2008 [cited by examiner]
KR 20220027666A · 2022 [cited by examiner]
KR 20220101650A · 2022 [cited by examiner]
WO WO2021094101A1 · 2021 [cited by examiner]
English Translation for JP-2008015638-A (Year: 2008). [cited by examiner]
An English-translated version of Japanese patent: JP2008015638A (by Kenta Morishima—published date: Jan. 24, 2008) (Year: 2008). [cited by examiner]
Basireddy, Karunakar Reddy. Runtime energy management of concurrent applications for multi-core platforms. Diss. University of Southampton, 2019. (Year: 2019). [cited by examiner]
Ichnowski, Jeffrey. Scaling Robot Motion Planning to Multi-Core Processors and the Cloud. Diss. The University of North Carolina at Chapel Hill, 2019. (Year: 2019). [cited by examiner]
Amarnath, Rakshith. Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems. Diss. Master Thesis, Delft University of Technology, 2012.[Online]. Available: http://resolver. tudelft. nl/uuid: 7fe80a02-fcf… [cited by examiner]
Kim, Sung Il, and Jong-Kook Kim. “A method to construct task scheduling algorithms for heterogeneous multi-core systems.” IEEE Access 7 (2019): 142640-142651. (Year: 2019). [cited by examiner]
European Patent Office; Search Report in related International Patent Application No. PCT/EP2020/080442 dated Feb. 9, 2021; 3 pages. [cited by applicant]
German Patent Office; Office Action in related German Patent Application No. 10 2019 217 427.2 dated Jul. 16, 2020; 7 pages. [cited by applicant]
Ulbrich, W.: Verlässliche Echtzeitsysteme. Lehrstuhl für Verteilte Systeme und Betriebssysteme, Friedrich Alexander-Universität Erlangen-Nürnberg; Apr. 28, 2016. [cited by applicant]
Chen, C.-I. H. u.a.: Task allocation and reallocation for fault tolerance in multicomputer systems. In IEEE Transactions an Aerospace and Electronic Systems, vol. 30, N. 4, Oct. 1994, S. 1094-1104. [cited by applicant]
Chinese Patent Office; Office Action in related Chinese Patent Application No. 2020800927228 dated Mar. 5, 2025; 8 pages. [cited by applicant]
European Patent Office; Examination Report in related European Patent Application No. 20 800 111.5 dated Nov. 4, 2024; 12 pages. [cited by applicant]