Storage device and memory system
A storage device is provided. The storage device includes a controller which receives a command from a host for instructing performance of a first computation, a non-volatile memory which stores a plurality of datasets, a buffer memory to which a first dataset among the plurality of datasets stored in the non-volatile memory is provided in response to the command, and an accelerator which performs the first computation corresponding to the command, using the first dataset provided to the buffer memory. The accelerator includes a memory access module which receives a first input query for instructing the first computation and the first dataset from the buffer memory, and a first computing module which is connected to the memory access module and determines first final candidate data corresponding to the first input query, using the first dataset.
1. A storage device comprising:
a controller which receives a command from a host for instructing performance of a first computation;
a non-volatile memory which stores a plurality of datasets;
a buffer memory, wherein a first dataset among the plurality of datasets stored in the non-volatile memory is provided to the buffer memory in response to the command; and
an accelerator which performs the first computation corresponding to the command, using the first dataset provided to the buffer memory,
wherein the accelerator comprises:
a memory access module which receives a first input query and a second input query for instructing the first computation and the first dataset from the buffer memory, wherein the first input query is different from the second input query;
a first computing module which is connected to the memory access module and determines first final candidate data corresponding to the first input query, using the first dataset received from the memory access module, wherein the first computing module calculates first vector distances between the first input query and entry points of the first dataset and retains the first vector distances that are shorter than a minimum distance as the first final candidate data; and
a second computing module which is connected to the memory access module and determines second final candidate data corresponding to the second input query, using the same first dataset received from the memory access module, wherein the second computing module calculates second other vector distances between the second input query and the entry points and retains the second vector distances that are shorter than a minimum distance as the second final candidate data,
wherein at least one of the computing modules:
maintains a visit list that tracks previously evaluated data points within the corresponding dataset, wherein a data point from the corresponding dataset is added to the visit list after its vector distance to the corresponding input query has been calculated;
maintains a candidate list comprising unvisited data points within the corresponding dataset, wherein a data point from the corresponding dataset is added to the candidate list when its vector distance to the corresponding input query is within a predefined distance threshold and has not been previously evaluated; and
selects the corresponding final candidate data based on data points in the candidate list that meet a predefined threshold,
wherein a block random-access memory (RAM) of the storage device includes a first block RAM storing an activated visit list and a second block RAM storing an initialized visit list.
2. The storage device of claim 1 , wherein the accelerator includes a Field Programmable Gate Array (FPGA).
3. The storage device of claim 1 , wherein the accelerator performs the first computation, using a hierarchical navigable small world (HNSW) search algorithm.
4. The storage device of claim 1 , wherein the memory access module includes a final calculator,
the first computing module includes a first calculator and a first comparator,
the first calculator performs a calculation based on the first input query, using the first dataset,
the first comparator determines the first final candidate data, using a result calculated by the first calculator, and
the final calculator determines a first final result data, using the first final candidate data determined by the first comparator.
5. The storage device of claim 4 , wherein the second computing module includes a second comparator and a second calculator,
the second calculator performs the calculation based on the second input query,
the second comparator determines the second final candidate data, using the result calculated by the second calculator, and
the final calculator determines a second final result data, using the second final candidate data determined by the second comparator.
6. The storage device of claim 5 , wherein the accelerator provides the host with first and second final result data.
7. The storage device of claim 1 , wherein the memory access module and the first computing module are connected by a first-in-first-out (FIFO) interface.
8. The storage device of claim 1 , wherein the non-volatile memory provides the first dataset to the buffer memory in a peer-to-peer communication, using Peripheral Component Interconnect express (PCle).
9. A memory system comprising:
a host which provides a command for instructing performance of a first computation; and
a first storage device to which the command is provided from the host,
wherein the first storage device comprises:
a first controller which controls the first storage device in response to the command;
a first non-volatile memory which stores a first dataset;
a first buffer memory which receives the first dataset from the first non-volatile memory in response to the command; and
a first accelerator which performs the first computation corresponding to the command, using the first dataset provided to the first buffer memory,
wherein the first accelerator comprises:
a first memory access module which receives a first input query and a second input query for instructing the first computation and the first dataset from the first buffer memory, wherein the first input query is different from the second input query;
a first computing module which is connected to the first memory access module and determines first final candidate data corresponding to the first input query, using the first dataset received from the first memory access module, wherein the first computing module calculates first vector distances between the first input query and entry points of the first dataset and retains the first vector distances that are shorter than a minimum distance as the first final candidate data; and
a second computing module which is connected to the first memory access module and determines second final candidate data corresponding to the second input query, using the same first dataset received from the memory access module, wherein the second computing module calculates second other vector distances between the second input query and the entry points and retains the second vector distances that are shorter than a minimum distance as the second final candidate data, and
wherein the first accelerator provides the host with the first final candidate data and the second final candidate data,
wherein at least one of the computing modules:
maintains a visit list that tracks previously evaluated data points within the corresponding dataset, wherein a data point from the corresponding dataset is added to the visit list after its vector distance to the corresponding input query has been calculated;
maintains a candidate list comprising unvisited data points within the corresponding dataset, wherein a data point from the corresponding dataset is added to the candidate list when its vector distance to the corresponding input query is within a predefined distance threshold and has not been previously evaluated; and
selects the corresponding final candidate data based on data points in the candidate list that meet a predefined threshold,
wherein a block random-access memory (RAM) of the memory system includes a first block RAM storing an activated visit list and a second block RAM storing an initialized visit list.
10. The memory system of claim 9 , further comprising:
a second storage device to which the command is provided from the host,
wherein the second storage device includes
a second controller which controls the second storage device in response to the command,
a second non-volatile memory which stores a second dataset different from the first dataset,
a second buffer memory which receives the second dataset from the second non- volatile memory in response to the command, and
a second accelerator which performs the first computation corresponding to the command, using the second dataset provided to the second buffer memory,
the second accelerator determines a second final candidate data corresponding to the first input query using the second dataset and provides the second final candidate data to the host, and
the host determines a final result data, using the first final candidate data and the second final candidate data.
11. The memory system of claim 9 , further comprising:
a second storage device to which the command is provided from the host,
wherein the second storage device includes
a second controller which controls the second storage device in response to the command,
a second non-volatile memory which stores the first dataset, and
a second buffer memory which receives the first dataset from the second non-volatile memory in response to the command, and
a second accelerator which receives a third input query from the second buffer memory, determines a third final candidate data corresponding to the third input query using the first dataset provided to the second buffer memory, and provides the third final candidate data to the host.
12. The memory system of claim 9 , wherein the host provides the command to the first storage device, using a Peripheral Component Interconnect express (PCle), and
the first accelerator provides the host with first final candidate data, using the PCle.
13. The memory system of claim 9 , wherein the first accelerator includes a Field Programmable Gate Array (FPGA).
14. The memory system of claim 9 , wherein the first non-volatile memory provides the first dataset to the first buffer memory in a peer-to-peer communication, using a Peripheral Component Interconnect express (PCle).
15. A storage device comprising:
a controller which receives a command from a host for instructing performance of a first computation and generates a control signal corresponding to the command;
a non-volatile memory which stores a first dataset and a second dataset;
a buffer memory which receives the first dataset and the second dataset from the non-volatile memory in a peer-to-peer communication in response to the control signal; and
an accelerator which generates a first final result data corresponding to the control signal, using the first dataset and the second dataset provided to the buffer memory,
wherein the accelerator comprises:
a memory access module which receives a first input query corresponding to the control signal, the first dataset, and the second dataset from the buffer memory;
a random-access-memory (RAM); and
a first computing module which performs the first computation in response to the memory access module receiving the first input query, wherein the first computation:
determines whether an index associated with the first input query is cached in the RAM;
dynamically retrieves the index from the non-volatile memory or the buffer memory when the index is not cached in the RAM;
retrieves a first data point from the first dataset and a second data point from the second dataset based on the index;
computes a distance between the first input query and each of the retrieved data points;
selects first final candidate data from the first dataset and second final candidate data from the second dataset, by evaluating the computed distances against a predefined similarity threshold; and
provides the memory access module with the first final candidate data and the second final candidate data,
wherein the memory access module generates the first final result data using the first final candidate data and the second final candidate data, and provides the first final result data to the host, and
wherein a block RAM of the storage device includes a first block RAM storing an activated visit list and a second block RAM storing an initialized visit list.
16. The storage device of claim 15 , wherein the accelerator includes a Field Programmable Gate Array (FPGA).
17. The storage device of claim 15 , wherein the accelerator further includes a second computing module,
wherein the memory access module is further provided with a second input query corresponding to the control signal from the buffer memory,
the second computing module generates a third final candidate data corresponding to the second input query using the first dataset, and generates a fourth final candidate data corresponding to the second input query using the second dataset,
the second computing module provides the memory access module with the third final candidate data and the fourth final candidate data, and
the memory access module generates a second final result data using the third final candidate data and the fourth final candidate data, and provides the second final result data to the host.
18. The storage device of claim 15 , wherein the first dataset includes a plurality of first data,
the second dataset includes a plurality of second data,
the first computing module determines a first nearest data having a vector distance nearest to the first input query among the plurality of first data, as the first final candidate data, and
the first computing module determines a second nearest data having a vector distance nearest to the first input query among the plurality of second data, as the second final candidate data.
19. The storage device of claim 15 , wherein the accelerator generates the first final result data, using a nearest neighbor search algorithm.
20. The storage device of claim 15 , wherein the RAM is a block RAM (BRAM).